M39P0R8070E2
M39P0R9070E2
256 or 512Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
128 Mbit Low Power SDRAM, 1.8V supply, Multi-Chip Package
Feature summary
■
Multi-Chip Package
– 1 die of 256 (16Mb x 16) or 512 Mbit (32Mb
x 16, Multiple Bank, Multi-Level, Burst)
Flash memory
– 1 die of 128 Mbit (4 Banks of 2Mb x16)
Low
Power Synchronous Dynamic RAM
Supply voltage
– V
DDF
= V
DDS
= V
DDQ
= 1.7 to 1.95V
– V
PPF
= 9V for fast program
Electronic signature
– Manufacturer Code: 20h
– 256 Mbit Device Code: 8818
– 512 Mbit Device Code: 8819
Package
– ECOPACK® (RoHS compliant)
Synchronous / Asynchronous Read
– Synchronous Burst Read mode:
108MHz, 66MHz
– Asynchronous Page Read mode
– Random Access: 96ns
Programming time
– 4.2µs typical Word program time using
Buffer Enhanced Factory Program
command
Memory organization
– Multiple Bank memory array: 32 Mbit
Banks (256Mb devices); 64 Mbit Banks
(512Mb devices)
– Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
FBGA
■
TFBGA105 (ZAD)
9 x 11mm
■
■
100,000 program/erase cycles per block
Security
– 64-bit unique device number
– 2112-bit user programmable OTP Cells
Block locking
– All Blocks locked at power-up
– Any combination of Blocks can be locked
with zero latency
– WP
F
for Block Lock-Down
– Absolute Write Protection with V
PPF
= V
SS
Common Flash Interface (CFI)
128 Mbit Synchronous Dynamic RAM
– Organized as 4 Banks of 2 MWords, each
16 bits wide
Synchronous Burst Read and Write
– Fixed burst lengths: 1, 2, 4, 8 Words or Full
Page
– Burst Types: Sequential and Interleaved
– Maximum Clock frequency: 104MHz
Automatic and controlled Precharge
Low power features:
– Partial Array Self Refresh (PASR)
– Automatic Temperature Compensated Self
Refresh (TCSR)
– Driver Strength (DS)
– Deep Power-Down Mode
Auto Refresh and Self Refresh
■
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Flash memory
■
■
LPSDRAM
■
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November 2007
Rev 2
1/24
www.numonyx.com
1
Contents
M39P0R8070E2, M39P0R9070E2
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash memory Chip Enable Input (E
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash memory Output Enable (G
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Write Enable (W
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Write Protect input (WP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Reset (RP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Deep Power-Down (DPD
F
) . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Latch Enable (L
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory Clock (K
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory Wait (WAIT
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LPSDRAM Chip Select (E
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LPSDRAM Column Address Strobe (CAS
S
) . . . . . . . . . . . . . . . . . . . . . . 12
LPSDRAM Row Address Strobe (RAS
S
) . . . . . . . . . . . . . . . . . . . . . . . . . 12
LPSDRAM Write Enable (W
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LPSDRAM Clock input (K
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LPSDRAM Clock Enable (KE
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LPSDRAM Lower/Upper Data Input/Output Mask (LDQM
S
/UDQM
S
) . . . 13
Flash memory V
DDF
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LPSDRAM V
DDS
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
DDQ
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash memory V
PPF
Program supply voltage . . . . . . . . . . . . . . . . . . . . . . 14
V
SS
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/24
M39P0R8070E2, M39P0R9070E2
Contents
5
6
7
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3/24
List of tables
M39P0R8070E2, M39P0R9070E2
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data . . . . . . . . . . 21
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4/24
M39P0R8070E2, M39P0R9070E2
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 20
5/24
京公网安备 11010802033920号
EEWORLD
