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SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES530E – DECEMBER 2003 – REVISED JUNE 2006
FEATURES
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
V
CC
Isolation Feature - If Either V
CC
Input Is at
GND, Both Ports Are in the High-Impedance
State
DIR Input Circuit Referenced to V
CCA
±12-mA
Output Drive at 3.3 V
I/Os Are 4.6-V Tolerant
I
off
Supports Partial-Power-Down Mode
Operation
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
•
Max Data Rates
– 500 Mbps (1.8-V to 3.3-V Translation)
– 320 Mbps (<1.8-V to 3.3-V Translation)
– 320 Mbps (Translate to 2.5 V or 1.8 V)
– 280 Mbps (Translate to 1.5 V)
– 240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
V
CCA
GND
A
1
6
V
CCB
DIR
B
V
CCA
GND
1
2
3
6
5
4
V
CCB
DIR
B
V
CCA
GND
A
1
2
3
6
5
4
V
CCB
DIR
B
A
GND
V
CCA
C1
3 4
C2
B
B1
2 5
B2
DIR
A1
1 6
A2
V
CCB
2
5
A
3
4
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The
SN74AVC1T45 is optimized to operate with V
CCA
/V
CCB
set at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
as
low as 1.2 V. The A port is designed to track V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. The
B port is designed to track V
CCB
. V
CCB
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40°C to 85°C
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1)
(2)
ORDERABLE PART NUMBER
SN74AVC1T45YEPR
Tape and reel
SN74AVC1T45YZPR
Tape and reel
Tape and reel
Reel of 4000
SN74AVC1T45DBVR
SN74AVC1T45DCKR
SN74AVC1T45DRLR
DT1_
TC_
TC_
_ _ _TC_
TOP-SIDE MARKING
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530E – DECEMBER 2003 – REVISED JUNE 2006
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits
data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when
the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess I
CC
and I
CCZ
.
The SN74AVC1T45 is designed so that the DIR input is powered by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, then both ports are in the high-impedance
state.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
(1)
INPUT
DIR
L
H
(1)
OPERATION
B data to A bus
A data to B bus
Input circuits of the data I/Os
always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
5
A
3
4
B
V
CCA
V
CCB
2
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www.ti.com
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530E – DECEMBER 2003 – REVISED JUNE 2006
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CCA
V
CCB
V
I
Supply voltage range
I/O ports (A port)
Input voltage range
(2)
I/O ports (B port)
Control inputs
V
O
V
O
I
IK
I
OK
I
O
Voltage range applied to any output in the high-impedance or
power-off state
(2)
Voltage range applied to any output in the high or low state
(2) (3)
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CCA
, V
CCB
, or GND
DBV package
θ
JA
Package thermal impedance
(4)
DCK package
DRL package
YEP/YZP package
T
stg
(1)
(2)
(3)
(4)
Storage temperature range
–65
A port
B port
A port
B port
V
I
< 0
V
O
< 0
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.6
4.6
4.6
4.6
4.6
4.6
V
CCA
+ 0.5
V
CCB
+ 0.5
–50
–50
±50
±100
165
259
142
123
150
°C
°C/W
V
V
mA
mA
mA
mA
V
UNIT
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530E – DECEMBER 2003 – REVISED JUNE 2006
www.ti.com
Recommended Operating Conditions
(1) (2) (3)
V
CCI
V
CCA
V
CCB
V
IH
Supply voltage
Supply voltage
1.2 V to 1.95 V
High-level
input voltage
Data inputs
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
V
IL
Low-level
input voltage
Data inputs
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
V
IH
High-level
input voltage
DIR
(referenced to V
CCA
)
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
V
IL
V
I
V
O
Low-level
input voltage
Input voltage
Output voltage
Active state
3-state
1.2 V
1.4 V to 1.6 V
I
OH
High-level output current
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
1.2 V
1.4 V to 1.6 V
I
OL
Low-level output current
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
∆t/∆v
T
A
(1)
(2)
(3)
Input transition rise or fall rate
Operating free-air temperature
–40
DIR
(referenced to V
CCA
)
1.95 V to 2.7 V
2.7 V to 3.6 V
0
0
0
V
CCA
×
0.65
1.6
2
V
CCA
×
0.35
0.7
0.8
3.6
V
CCO
3.6
–3
–6
–8
–9
–12
3
6
8
9
12
5
85
ns/V
°C
mA
mA
V
V
V
V
V
CCO
MIN
1.2
1.2
V
CCI
×
0.65
1.6
2
V
CCI
×
0.35
0.7
0.8
V
V
MAX
3.6
3.6
UNIT
V
V
V
CCI
is the V
CC
associated with the input port.
V
CCO
is the V
CC
associated with the output port.
All unused data inputs of the device must be held at V
CCI
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
4
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