PCA9517A
Level translating I
2
C-bus repeater
Rev. 02 — 5 May 2008
Product data sheet
1. General description
The PCA9517A is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I
2
C-bus or SMBus applications.
While retaining all the operating modes and features of the I
2
C-bus system during the
level shifts, it also permits extension of the I
2
C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using
the PCA9517A enables the system designer to isolate two halves of a bus for both voltage
and capacitance. The SDA and SCL pins are overvoltage tolerant and are
high-impedance when the PCA9517A is unpowered.
The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus port A drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V
LOW on the port A which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the port B PCA9517A I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B),
or PCA9518. Port A of two or more PCA9517As can be connected together, however, to
allow a star topography with port A on the common bus, and port A can be connected
directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can
be connected in series, port A to port B, with no build-up in offset voltage with only time of
flight delays to consider.
The PCA9517A drivers are not enabled unless V
CC(A)
is above 0.8 V and V
CC(B)
is above
2.5 V. The EN pin can also be used to turn the drivers on and off under system control.
Caution should be observed to only change the state of the enable pin when the bus is
idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This
prevents a lock-up condition from occurring. The output pull-down on port A drives a hard
LOW and the input level is set at 0.3V
CC(A)
to accommodate the need for a lower
LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
Table 1.
Parameter
electrostatic discharge, HBM
electrostatic discharge, MM
[1]
[2]
PCA9517 and PCA9517A comparison
PCA9517
[1]
> 2 kV
> 200 V
PCA9517A
[2]
> 5.5 kV
> 450 V
Will continue to be supported for existing designs and new designs where migrating to the PCA9517A is not
possible.
Highly recommended for all new designs due to improved I
2
C-bus operation and ESD performance.
NXP Semiconductors
PCA9517A
Level translating I
2
C-bus repeater
2. Features
I
2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device
I
Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
I
Footprint and functional replacement for PCA9515/15A
I
I
2
C-bus and SMBus compatible
I
Active HIGH repeater enable input
I
Open-drain input/outputs
I
Lock-up free operation
I
Supports arbitration and clock stretching across the repeater
I
Accommodates Standard-mode and Fast-mode I
2
C-bus devices and multiple masters
I
Powered-off high-impedance I
2
C-bus pins
I
Port A operating supply voltage range of 0.9 V to 5.5 V
I
Port B operating supply voltage range of 2.7 V to 5.5 V
I
5 V tolerant I
2
C-bus and enable pins
I
0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater)
I
ESD protection exceeds 5500 V HBM per JESD22-A114, 450 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: SO8 and TSSOP8
3. Ordering information
Table 2.
Ordering information
T
amb
=
−
40
°
C to +85
°
C.
Type number
PCA9517AD
Topside
mark
PA9517A
Package
Name
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
PCA9517ADP 9517A
[1]
Also known as MSOP8.
TSSOP8
[1]
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
PCA9517A_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 5 May 2008
2 of 19
NXP Semiconductors
PCA9517A
Level translating I
2
C-bus repeater
4. Functional diagram
V
CC(A)
V
CC(B)
PCA9517A
SDAA
SDAB
SCLA
V
CC(B)
pull-up
resistor
SCLB
EN
002aad465
GND
Fig 1.
Functional diagram of PCA9517A
5. Pinning information
5.1 Pinning
V
CC(A)
SCLA
SDAA
GND
1
2
8
7
V
CC(B)
SCLB
SDAB
EN
V
CC(A)
SCLA
SDAA
GND
1
2
3
4
002aad467
8
7
V
CC(B)
SCLB
SDAB
EN
PCA9517AD
3
4
002aad466
6
5
PCA9517ADP
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
(MSOP8)
5.2 Pin description
Table 3.
Symbol
V
CC(A)
SCLA
SDAA
GND
EN
SDAB
SCLB
V
CC(B)
PCA9517A_2
Pin description
Pin
1
2
3
4
5
6
7
8
Description
port A supply voltage (0.9 V to 5.5 V)
serial clock port A bus
serial data port A bus
supply ground (0 V)
active HIGH repeater enable input
serial data port B bus
serial clock port B bus
port B supply voltage (2.7 V to 5.5 V)
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 5 May 2008
3 of 19
NXP Semiconductors
PCA9517A
Level translating I
2
C-bus repeater
6. Functional description
Refer to
Figure 1 “Functional diagram of PCA9517A”.
The PCA9517A enables I
2
C-bus or SMBus translation down to V
CC(A)
as low as 0.9 V
without degradation of system performance. The PCA9517A contains two bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I
2
C-bus or SMBus. All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (V
CC(B)
and/or V
CC(A)
= 0 V). The PCA9517A includes a power-up circuit that keeps the output
drivers turned off until V
CC(B)
is above 2.5 V and the V
CC(A)
is above 0.8 V. V
CC(B)
and
V
CC(A)
can be applied in any sequence at power-up. After power-up and with the enable
(EN) HIGH, a LOW level on port A (below 0.3V
CC(A)
) turns the corresponding port B driver
(either SDA or SCL) on and drives port B down to about 0.5 V. When port A rises above
0.3V
CC(A)
, the port B pull-down driver is turned off and the external pull-up resistor pulls
the pin HIGH. When port B falls first and goes below 0.3V
CC(B)
the port A driver is turned
on and port A pulls down to 0 V. The port B pull-down is not enabled unless the port B
voltage goes below 0.4 V. If the port B low voltage does not go below 0.5 V, the port A
driver will turn off when port B voltage is above 0.7V
CC(B)
. If the port B low voltage goes
below 0.4 V, the port B pull-down driver is enabled and port B will only be able to rise to
0.5 V until port A rises above 0.3V
CC(A)
, then port B will continue to rise being pulled up by
the external pull-up resistor. The V
CC(A)
is only used to provide the 0.3V
CC(A)
reference to
the port A input comparators and for the power good detect circuit. The PCA9517A logic
and all I/Os are powered by the V
CC(B)
pin.
6.1 Enable
The EN pin is active HIGH with an internal pull-up to V
CC(B)
and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an
I
2
C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I
2
C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I
2
C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode and Fast
mode I
2
C-bus devices in addition to SMBus devices. Standard mode I
2
C-bus devices only
specify 3 mA output drive; this limits the termination current to 3 mA in a generic I
2
C-bus
system where Standard-mode devices and multiple masters are possible. Under certain
conditions higher termination currents can be used.
Please see Application Note
AN255, I
2
C/SMBus Repeaters, Hubs and Expanders
for
additional information on sizing resistors and precautions when using more than one
PCA9517A in a system or using the PCA9517A in conjunction with other bus buffers.
PCA9517A_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 5 May 2008
4 of 19
NXP Semiconductors
PCA9517A
Level translating I
2
C-bus repeater
7. Application design-in information
A typical application is shown in
Figure 4.
In this example, the system master is running
on a 3.3 V I
2
C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.
Master devices can be placed on either bus.
3.3 V
1.2 V
10 kΩ
10 kΩ
10 kΩ
10 kΩ
V
CC(B)
SDA
SCL
BUS
MASTER
400 kHz
SDAB
SCLB
V
CC(A)
SDAA
SCLA
SDA
SCL
SLAVE
400 kHz
PCA9517A
EN
bus B
bus A
002aad468
Fig 4.
Typical application
The PCA9517A is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
When port A of the PCA9517A is pulled LOW by a driver on the I
2
C-bus, a comparator
detects the falling edge when it goes below 0.3V
CC(A)
and causes the internal driver on
port B to turn on, causing port B to pull down to about 0.5 V. When port B of the
PCA9517A falls, first a CMOS hysteresis type input detects the falling edge and causes
the internal driver on port A to turn on and pull the port A pin down to ground. In order to
illustrate what would be seen in a typical application, refer to
Figure 8
and
Figure 9.
If the
bus master in
Figure 4
were to write to the slave through the PCA9517A, waveforms
shown in
Figure 8
would be observed on the A bus. This looks like a normal I
2
C-bus
transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn
off of the acknowledge signals are slightly delayed.
On the B bus side of the PCA9517A, the clock and data lines would have a positive offset
from ground equal to the V
OL
of the PCA9517A. After the 8
th
clock pulse, the data line will
be pulled to the V
OL
of the slave device which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517A for a short delay while the A bus side rises above 0.3V
CC(A)
then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517A (V
IL
) be at or below 0.4 V to be
recognized by the PCA9517A and then transmitted to the A bus side.
Multiple PCA9517A port A sides can be connected in a star configuration (Figure
5),
allowing all nodes to communicate with each other.
Multiple PCA9517As can be connected in series (Figure
6)
as long as port A is connected
to port B. I
2
C-bus slave devices can be connected to any of the bus segments. The
number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
PCA9517A_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 5 May 2008
5 of 19
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