87972DYI-147T datasheet, PDF - EEWORLD Datasheet

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87972DYI-147T: DescriptionProcessor Specific Clock Generator, 150MHz, PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52; CategoryThe embedded processor and controller Microcontrollers and processors; File Size303KB，14 Pages; ManufacturerIDT (Integrated Device Technology)

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87972DYI-147T Overview

Processor Specific Clock Generator, 150MHz, PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52

87972DYI-147T Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
Contacts	52
Reach Compliance Code	not_compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G52
JESD-609 code	e0
length	10 mm
Humidity sensitivity level	3
Number of terminals	52
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	150 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP52,.47SQ
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Master clock/crystal nominal frequency	150 MHz
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	250 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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Integrated

Circuit

Systems, Inc.

ICS87972I-147

KEW

, 1-

-12

LVCMOS/LVTTL C

LOCK

ULTIPLIER

ERO

ELAY

UFFER

EATURES

•

Fully integrated PLL

•

14 LVCMOS/LVTTL outputs; (12)clocks, (1)feedback, (1)sync

•

Selectable crystal oscillator interface or LVCMOS/LVTTL

reference clock inputs

•

CLK0, CLK1 can accept the following input levels:

LVCMOS or LVTTL

•

Output frequency range: 10MHz to 150MHz

•

VCO range: 240MHz to 500MHz

•

Output skew: 200ps (maximum)

•

Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)

•

Full 3.3V operating supply

•

-40°C to 85°C ambient operating temperature

•

Pin compatible with MPC972

•

Compatible with PowerPC™ and Pentium™ Microprocessors

ENERAL

ESCRIPTION

ICS

HiPerClockS™

The ICS87972I-147 is a low skew, LVCMOS/LVTTL

Clock Generator and a member of the HiPerClock™

family of High Performance Clock Solutions from

ICS.The ICS87972I-147 has three selectable inputs

and provides 14 LVCMOS/LVTTL outputs.

The ICS87972I-147 is a highly flexible device. Using the crystal

oscillator input, it can be used to generate clocks for a system.

All of these clocks can be the same frequency or the device can

be configured to generate up to three different frequencies among

the three output banks. Using one of the single ended inputs, the

ICS87972I-147 can be used as a zero delay buffer/multiplier/

divider in clock distribution applications.

The three output banks and feedback output each have their

own output dividers which allows the device to generate a

multitude of different bank frequency ratios and output-to-input

frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)

can be selected to be inverting or non-inverting. The output

frequency range is

10MHz

to 150MHz. Input frequency range is

6MHz to 150MHz.

The ICS87972I-147 also has a QSYNC output which can be

used or system synchronization purposes. It monitors Bank A

and Bank C outputs and goes low one period

of the faster clock

prior to coincident rising edges of Bank A and Bank C clocks.

QSYNC then goes high again when the coincident rising edges

of Bank A and Bank C occur. This feature is used primarily in

applications where Bank A and Bank C are running at different

frequencies, and is particularly useful when they are running at

non-integer multiples of one another.

Example Applications:

System Clock generator:

Use a 16.66 MHz Crystal to

generate eight 33.33MHz copies for PCI and four 100MHz

copies for the CPU or PCI-X.

Line Card Multiplier:

Multiply 19.44MHz from a back plane

to 77.76MHz for the line Card ASICs and Serdes.

Zero Delay buffer for Synchronous memory:

Fan out up

to twelve 100MHz copies from a memory controller ref-

erence clock to the memory chips on a memory module

with zero delay.

SSIGNMENT

FSEL_FB0

EXT_FB

GNDO

DDO

QB0

QB1

QB2

QB3

QFB

FSEL_B1

FSEL_B0

FSEL_A1

FSEL_A0

QA3

DDO

QA2

GNDO

QA1

DDO

QA0

GNDO

VCO_SEL

39 38 37 36 35 34 33 32 31 30 29 28 27

GNDI

FSEL_FB1

QSYNC

GNDO

QC0

DDO

QC1

FSEL_C0

FSEL_C1

QC2

DDO

QC3

GNDO

INV_CLK

ICS87972I-147

nMR/OE

FRZ_CLK

FRZ_DATA

5 6

FSEL_FB2

PLL_SEL

7 8

REF_SEL

CLK_SEL

9 10 11 12 13

CLK0

CLK1

XTAL1

XTAL2

DDA

52-Lead LQFP

10mm x 10mm x 1.4mm package body

Y package

Top View

87972DYI-147

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 24, 2009

87972DYI-147T Related Products

	87972DYI-147T	87972DYI-147
Description	Processor Specific Clock Generator, 150MHz, PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52	Processor Specific Clock Generator, 150MHz, PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	QFP	QFP
package instruction	10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52	10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
Contacts	52	52
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
JESD-30 code	S-PQFP-G52	S-PQFP-G52
JESD-609 code	e0	e0
length	10 mm	10 mm
Humidity sensitivity level	3	3
Number of terminals	52	52
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	150 MHz	150 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP
Encapsulate equivalent code	QFP52,.47SQ	QFP52,.47SQ
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240	240
power supply	3.3 V	3.3 V
Master clock/crystal nominal frequency	150 MHz	150 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm
Maximum slew rate	250 mA	250 mA
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	20	20
width	10 mm	10 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC

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