FemtoClock
®
Crystal-to-LVPECL 375MHz
Frequency Margining Synthesizer
G
ENERAL
D
ESCRIPTION
The
843201-375
is a low phase-noise frequency margining
synthesizer. In the default mode, the device nominally generates a
375MHz
LVPECL output clock signal from a 25MHz crystal input.
There is also a frequency margining mode available where the
device can be configured, using control pins, to vary the output
frequency up or down from nominal by 5%. The
843201-375
is
provided in a 16-pin TSSOP package.
843201-375
DATASHEET
F
EATURES
•
One
375MHz
nominal LVPECL output
•
Crystal oscillator interface designed for 25MHz, 18pF parallel
resonant crystal
• Output frequency can be varied ± 5% from nominal
• VCO range: 700MHz -
800MHz
• RMS phase jitter @
375MHz,
using a 25MHz crystal
(12kHz - 20MHz): 0.72ps (typical) @
3.3V
• Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
•
Functional replacement part
8T49N241-dddNLGI
B
LOCK
D
IAGRAM
nPLL_SEL
Pulldown
P
IN
A
SSIGNMENT
V
CC
MODE
nc
XTAL_IN
XTAL_OUT
MARGIN
V
EE
nc
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
nQ
V
CCO
V
CC
V
EE
MR
nPLL_SEL
nc
0
XTAL_IN
25MHz
1
Q
0
OSC
XTAL_OUT
Predivider
÷2
1
Phase
Detector
VCO
700 -
800MHz
÷2
nQ
843201-375
÷30
(÷57, ÷63)
MODE
MARGIN
MR
Pulldown
Pulldown
Pulldown
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
843201-375 REVISION A 8/21/15
1
©2015 Integrated Device Technology, Inc.
843201-375 DATA SHEET
F
UNCTIONAL
D
ESCRIPTION
The
843201-375
features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A 25MHz fundamental crystal is used as the input to the on chip
oscillator. In regular mode, the 25MHz crystal frequency is applied
directly to the phase detector. In frequency margining mode, the
25MHz crystal frequency is divided by 2 and a 12.5MHz reference
frequency is applied to the phase detector. The VCO of the PLL
operates over a range of 700MHz to
800MHz.
The output of the M
divider is also applied to the phase detector. The default mode for
the
843201-375
is a nominal
375MHz
output. The nominal output
frequency can be changed by placing the device into the margining
mode using the mode pin and using the margin pin to change the M
feedback divider. Frequency margining mode operation occurs when
the MODE input is HIGH. The phase detector and the M divider force
the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. The output of the VCO is scaled by
an output divider prior to being sent to the LVPECL output buffer. The
divider provides a 50% output duty cycle. The relationship between
the crystal input frequency, the M divider, the VCO frequency and
the output frequency is provided in Table 1. When changing back
from frequency margining mode to nominal mode, the device will
return to the default nominal configuration described above.
T
ABLE
1. F
REQUENCY
M
ARGIN
F
UNCTION
T
ABLE
MODE
1
0
1
MARGIN
0
X
1
XTAL (MHz)
25
25
25
Pre-Divider (P)
2
none
2
Reference
Frequency (MHz)
12.5
25
12.5
Feedback
Divider
57
30
63
VCO (MHz)
712.5
750
787.5
% Change
-5.0
Nom. Mode
5.0
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
2
REVISION A 8/21/15
843201-375 DATA SHEET
T
ABLE
2. P
IN
D
ESCRIPTIONS
Number
1, 13
2
3, 8, 9
4, 5
6
7, 12
10
Name
V
CC
MODE
Type
Power
Input
Description
Positive supply pins.
MODE pin. LOW = default mode. HIGH = frequency margining mode.
Pulldown
LVCMOS/LVTTL interface levels.
No connect.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Sets
the frequency margin to ±5% in frequency margining mode.
Pulldown
See
Table 1. LVCMOS/LVTTL interface levels.
Negative supply pins.
PLL select pin. When HIGH, PLL is bypassed and input is fed directly to
Pulldown the output dividers. When LOW, PLL is enabled.
LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go low and the inverted output nQ
Pulldown
to go high. When logic LOW, the internal dividers and the output is en-
abled. LVCMOS/LVTTL interface levels.
Output supply pin.
Differential output pair. LVPECL interface levels.
nc
Unused
XTAL_IN, XTAL_
Input
OUT
Margin
V
EE
nPLL_SEL
Input
Power
Input
11
14
15, 16
MR
V
CCO
nQ, Q
Input
Power
Output
NOTE: Pulldown refers to internal input resistors.
See
Table 2, Pin Characteristics, for typical values.
T
ABLE
3. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
T
ABLE
4. M
ODE
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
MODE
0
1
Condition
Q, nQ
Default Mode
Frequency Margining Mode
REVISION A 8/21/15
3
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply
Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge
Current
Package Thermal Impedance,
θ
JA
Storage
Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
99.9°C/W
(0 lfpm)
-65°C to 150°C
N OT E :
S
t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
=
3.3V±5%,
T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCO
I
EE
I
CC
I
CCO
Parameter
Positive
Supply
Voltage
Output
Supply
Voltage
Power
Supply
Current
Power
Supply
Current
Output
Supply
Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
108
96
12
Units
V
V
mA
mA
mA
T
ABLE
5B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
=
3.3V±5%,V
CCO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCO
I
EE
I
CC
I
CCO
Parameter
Positive
Supply
Voltage
Output
Supply
Voltage
Power
Supply
Current
Power
Supply
Current
Output
Supply
Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
108
96
12
Units
V
V
mA
mA
mA
T
ABLE
5C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCO
I
EE
I
CC
I
CCO
Parameter
Positive
Supply
Voltage
Output
Supply
Voltage
Power
Supply
Current
Power
Supply
Current
Output
Supply
Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
101
95
6
Units
V
V
mA
mA
mA
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
4
REVISION A 8/21/15
843201-375 DATA SHEET
T
ABLE
5D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
MARGIN, MODE,
nPLL_SEL, MR
MARGIN, MODE,
nPLL_SEL, MR
Test Conditions
V
CC
=
3.3V
V
CC
= 2.5V
V
CC
=
3.3V
V
CC
= 2.5V
V
CC
= V
IN
=
3.465
or 2.625V
V
CC
=
3.465V
or 2.625V,
V
IN
= 0V
-5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
T
ABLE
5E. LVPECL DC C
HARACTERISTICS
,
T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage
Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
- 2V.
T
ABLE
6. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent
Series
Resistance (ESR)
Shunt
Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
NOTE: It is not recommended to overdrive the crystal input with an external clock.
Test Conditions
Minimum
Typical Maximum
25
50
7
300
Units
MHz
Ω
pF
µW
Fundamental
REVISION A 8/21/15
5
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
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