8405201QA datasheet, PDF - EEWORLD Datasheet

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8405201QA: Description16-BIT, 5MHz, MICROPROCESSOR, CDIP40; CategoryThe embedded processor and controller Microcontrollers and processors; File Size437KB，36 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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8405201QA Overview

16-BIT, 5MHz, MICROPROCESSOR, CDIP40

8405201QA Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	DIP
package instruction	,
Contacts	40
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Address bus width	20
bit size	16
boundary scan	NO
maximum clock frequency	5 MHz
External data bus width	16
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	R-CDIP-T40
low power mode	YES
Number of DMA channels
Number of external interrupt devices	2
Number of serial I/Os
Number of terminals	40
On-chip data RAM width
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
RAM (number of words)	0
speed	5 MHz
Maximum slew rate	50 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal location	DUAL
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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80C86

CMOS 16-Bit Microprocessor

Description

The Intersil 80C86 high performance 16-bit CMOS CPU is

manufactured using a self-aligned silicon gate CMOS pro-

cess (Scaled SAJI IV). Two modes of operation, minimum

for small systems and maximum for larger applications such

as multiprocessing, allow user configuration to achieve the

highest performance level. Full TTL compatibility (with the

exception of CLOCK) and industry standard operation allow

use of existing NMOS 8086 hardware and software designs.

March 1997

Features

• Compatible with NMOS 8086

• Completely Static CMOS Design

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8MHz (80C86-2)

• Low Power Operation

- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500µA Max

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ

• 1MByte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary, or Decimal

- Multiply and Divide

• Wide Operating Temperature Range

- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0

C to +70

- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to +85

- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55

C to +125

Ordering Information

PACKAGE

PDIP

TEMP. RANGE

C to +70

5MHz

CP80C86

8MHz

PKG.

NO.

CP80C86-2 E40.6

IP80C86-2

E40.6

-40 C to +85 C lP80C86

PLCC

+70

CS80C86

-40

C to +85

C lS80C86

CERDIP

C to +70

CD80C86

-40

C to +85

C ID80C86

CS80C86-2 N44.65

IS80C86-2

N44.65

CD80C86-2 F40.6

ID80C86-2

F40.6

-55

C to +125

C MD80C86/B MD80C86-

2/B

SMD#

CLCC

SMD#

-55

C to +125

C MR80C86/B MR80C86-

2/B

-55

C to +125

C 8405201QA 8405202QA F40.6

J44.A

-55

C to +125

C 8405201XA 8405202XA J44.A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

FN2957.1

141

80C86

Pin Description

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

NUMBER

2-16, 39

SYMBOL

AD15-AD0

TYPE

I/O

DESCRIPTION

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and

data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-

D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory

or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-

dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-

ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”

or “grant sequence”.

ADDRESS/STATUS: During T1, these are the four most significant address lines for memory

operations. During I/O operations these lines are LOW. During memory and I/O operations, sta-

tus information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status

of the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3

are encoded as shown.

This information indicates which segment register is presently being used for data accessing.

These lines are held at high impedance to the last valid logic level during local bus “hold ac-

knowledge” or “grant sequence”.

CHARACTERISTICS

Alternate Data

Stack

Code or None

Data

A19/S6

A18/S5

A17/S4

A16/S3

35-38

BHE/S7

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to

enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devic-

es tied to the upper half of the bus would normally use BHE to condition chip select functions.

BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be

transferred on the high portion of the bus. The S7 status information is available during T2, T3

and T4. The signal is active LOW, and is held at high impedance to the last valid logic level dur-

ing interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW dur-

ing T1 for the first interrupt acknowledge cycle.

BHE

CHARACTERISTICS

Whole Word

Upper Byte From/to Odd Address

Lower Byte From/to Even address

None

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-

pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on

the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-

teed to remain HIGH in T2 until the 80C86 local bus has floated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-

quence”.

READY

READY: is the acknowledgment from the addressed memory or I/O device that will complete the

data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gen-

erator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.

Correct operation is not guaranteed if the Setup and Hold Times are not met.

144

80C86

Pin Description

(Continued)

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

NUMBER

SYMBOL

INTR

TYPE

DESCRIPTION

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle

of each instruction to determine if the processor should enter into an interrupt acknowledge op-

eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-

ory. It can be internally masked by software resetting the interrupt enable bit.

lNTR is internally synchronized. This signal is active HIGH.

TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each

clock cycle on the leading edge of CLK.

NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A

subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is

not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the

end of the current instruction. This input is internally synchronized.

RESET: causes the processor to immediately terminate its present activity. The signal must

transition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execu-

tion, as described in the Instruction Set description, when RESET returns LOW. RESET is inter-

nally synchronized.

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a

33% duty cycle to provide optimized internal timing.

VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for de-

coupling.

GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is rec-

ommended for decoupling.

TEST

NMI

RESET

CLK

VCC

GND

1, 20

MN/MX

MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are

discussed in the following sections.

Minimum Mode System

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V

). Only the pin functions which are unique to

minimum mode are described; all other pin functions are as described below.

NUMBER

SYMBOL

M/IO

TYPE

DESCRIPTION

STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-

ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains

valid until the final T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic

one during local bus “hold acknowledge”.

WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending

on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active

LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is

active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never

floated.

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the

82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.

Note that ALE is never floated.

INTA

ALE

145

8405201QA Related Products

	8405201QA	IS80C86	8405202XA	8405201XA	MR80C86-2/B	MR80C86/B	IP80C86	IP80C86-2	MD80C86/B
Description	16-BIT, 5MHz, MICROPROCESSOR, CDIP40	16-BIT, 5MHz, MICROPROCESSOR, PQCC44, PLASTIC, LCC-44	16-BIT, 8MHz, MICROPROCESSOR, CQCC44, CERAMIC, LCC-44	16-BIT, 5MHz, MICROPROCESSOR, CQCC44	16-BIT, 8MHz, MICROPROCESSOR, CQCC44, CERAMIC, LCC-44	16-BIT, 5MHz, MICROPROCESSOR, CQCC44	16-BIT, 5MHz, MICROPROCESSOR, PDIP40	16-BIT, 8MHz, MICROPROCESSOR, PDIP40	16-BIT, 5MHz, MICROPROCESSOR, CDIP40, CERDIP-40
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation
package instruction	,	PLASTIC, LCC-44	CERAMIC, LCC-44	CERAMIC, LCC-44	CERAMIC, LCC-44	CERAMIC, LCC-44	DIP, DIP40,.6	DIP, DIP40,.6	DIP, DIP40,.6
Reach Compliance Code	unknown	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
Address bus width	20	20	20	20	20	20	20	20	20
bit size	16	16	16	16	16	16	16	16	16
boundary scan	NO	NO	NO	NO	NO	NO	NO	NO	NO
maximum clock frequency	5 MHz	5 MHz	8 MHz	5 MHz	8 MHz	5 MHz	5 MHz	8 MHz	5 MHz
External data bus width	16	16	16	16	16	16	16	16	16
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Integrated cache	NO	NO	NO	NO	NO	NO	NO	NO	NO
JESD-30 code	R-CDIP-T40	S-PQCC-J44	S-CQCC-N44	S-CQCC-N44	S-CQCC-N44	S-CQCC-N44	R-PDIP-T40	R-PDIP-T40	R-GDIP-T40
low power mode	YES	YES	YES	YES	YES	YES	YES	YES	YES
Number of terminals	40	44	44	44	44	44	40	40	40
Maximum operating temperature	125 °C	85 °C	125 °C	125 °C	125 °C	125 °C	85 °C	85 °C	125 °C
Minimum operating temperature	-55 °C	-40 °C	-55 °C	-55 °C	-55 °C	-55 °C	-40 °C	-40 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
Package shape	RECTANGULAR	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	IN-LINE	IN-LINE	IN-LINE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
speed	5 MHz	5 MHz	8 MHz	5 MHz	8 MHz	5 MHz	5 MHz	8 MHz	5 MHz
Maximum slew rate	50 mA	50.5 mA	80 mA	50 mA	80.5 mA	50 mA	50 mA	80 mA	50.5 mA
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.25 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.75 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	YES	YES	YES	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	INDUSTRIAL	MILITARY	MILITARY	MILITARY	MILITARY	INDUSTRIAL	INDUSTRIAL	MILITARY
Terminal form	THROUGH-HOLE	J BEND	NO LEAD	NO LEAD	NO LEAD	NO LEAD	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal location	DUAL	QUAD	QUAD	QUAD	QUAD	QUAD	DUAL	DUAL	DUAL
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Parts packaging code	DIP	LCC	LCC	LCC	LCC	LCC	DIP	-	DIP
Contacts	40	44	44	44	44	44	40	-	40
ECCN code	3A001.A.2.C	-	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	-	-	3A001.A.2.C
Number of external interrupt devices	2	-	-	2	-	2	2	2	-
Is it Rohs certified?	-	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
JESD-609 code	-	e0	e0	-	e0	e0	e0	e0	e0
encapsulated code	-	QCCJ	QCCN	-	QCCN	QCCN	DIP	DIP	DIP
Encapsulate equivalent code	-	LDCC44,.7SQ	LCC44,.65SQ	-	LCC44,.65SQ	LCC44,.65SQ	DIP40,.6	DIP40,.6	DIP40,.6
power supply	-	5 V	5 V	-	5 V	5 V	5 V	5 V	5 V
Terminal surface	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb) - hot dipped	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal pitch	-	1.27 mm	1.27 mm	-	1.27 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm

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