BUS-61553-80Y datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> BUS-61553-80Y

BUS-61553-80Y: DescriptionMicro Peripheral IC; CategoryThe embedded processor and controller Microcontrollers and processors; File Size50KB，4 Pages; ManufacturerData Device Corporation

Download Datasheet Parametric View All

BUS-61553-80Y Overview

Micro Peripheral IC

BUS-61553-80Y Parametric

Parameter Name	Attribute value
Maker	Data Device Corporation
package instruction	,
Reach Compliance Code	unknown

Preview

Download Datasheet

View All

BUS-61553

MIL-STD-1553 ADVANCED INTEGRATED

MUX (AIM ) HYBRID

ALSO

SEE

IDE

R’S GU

USE

DESCRIPTION

DDC’s

BUS-61553

Advanced

Integrated Mux (AIM) Hybrid is a

complete

MIL-STD-1553

Bus

Controller (BC), Remote Terminal

Unit (RTU), and Bus Monitor (MT)

device. Packaged in a single 78-pin

DIP package, the BUS-61553 con-

tains dual low-power transceivers,

complete BC/RT/MT protocol logic, a

MIL-STD-1553-to-host interface unit

and 8K x 16 RAM.

Using an industry standard dual

transceiver and standard status and

control signals, the BUS-61553 sim-

plifies system integration at both the

MIL-STD-1553 and host processor

interface levels.

All 1553 operations are controlled

through the CPU access to the

shared 8K x 16 RAM. To ensure

maximum design flexibility, memory

control lines are provided for attach-

ing external RAM to the BUS-61553

address and data buses and for dis-

abling internal memory; the total

combined memory space can be

expanded to 64K x 16. All 1553 trans-

fers are entirely memory-mapped;

thus the CPU interface requires

minimal hardware and/or software

support.

The BUS-61553 operates over the

full military -55°C to +125°C temper-

ature range. Available screened to

MIL-PRF-38534, the BUS-61553 is

ideal for demanding military and

industrial microprocessor-to-1553

interface applications.

FEATURES

• Fully Intergrated Terminal

Including:

–Dual Transceiver

–BC/RT/MT Protocol

–Memory Management Unit

–Processor lnterface Logic

–8K x 16 RAM

• CMOS and Bipolar Technologies

• Internal Interrupt Status and Time

Tag Registers

• High Reliability

• 883B Processing Available

BUS-25679

DATA

BUS A

TRANSCEIVER A

TX INH

CONTENTION

RESOLVER

INTERRUPT

GENERATOR

CLOCK IN

CHANNEL A

ENCODER/

DECODER

MEMORY

TIMING

CPU

TIMING

MSTRCLR

SELECT

STRBD

READYD

RD/WR

MEM/REG

EXTEN

EXTLD

INT

TRANSFORMER A

768

µs

TIME OUT

PROTOCOL

CONTROLLER

A15-A00

BUS-25679

DATA

BUS B

TX INH

TRANSCEIVER B

D15-D00

TRANSFORMER B

CHANNEL B

ENCODER/

DECODER

8K x 16

SHARED RAM

PARITY

CHECKER

RT ADDR

RTAD0

RTAD1

RTAD2

RTAD3

RTAD4

RTAD P

RTPARERR

RAM

FIGURE 1. BU-61553 BLOCK DIAGRAM

Recommended Resources

Quartz oscillator diseases circuit and calculation-parallel crystal oscillator

Automatic intermittent forward and reverse control circuit for elevator traction machine simulation test

Another kind of interlocking control circuit for two electric motors

Pipe wire automatic feeding and weighing circuit

555 rice cooker automatic power regulator circuit

OPA541 basic application circuit

A collection of commonly used op amp circuits: A collection of commonly used op amp circuitsAuthor: fsj...; fighting Analog electronics

Question: How can a single-chip microcomputer detect when a telephone is hung up?: When a call ends, the caller or the called party hangs up, and the switch sends a busy signal to the other party. After a period of time, the busy signal needs to be cancelled. How can I use a single-...; 678 RF/Wirelessly

About TMS320C64x+ DSP-----Cache Optimization: 1. Cache performance characteristics Excellent cache performance depends largely on the reuse of cache lines, and this is also the main goal of optimization. This is generally achieved through proper ...; Aguilera Microcontroller MCU

Can only see but not read articles: This short passage is understandable, but if you read it to someone else, he will not understand it anyway! "The Story of Shi Shi Eating Lions" Shi Shi, a poet in the Stone Chamber, loves lions and vo...; shuangshumei Talking

Urgent! Testing the SDRAM module of DM642, the memory after 0x8000000 is "--": Urgent! When testing the SDRAM module of DM642, the memory after 0x8000000 is "--", is it because the data is not written? The program result shows that the SDRAM works well! It is shown in the pictur...; xuan_EEer DSP and ARM Processors

Show off the Valentine's Day gift I exchanged for my wife with E coins: Valentine's Day is coming. As an electrician, I am not very romantic, so I bought some practical things. I found that my wife's bag was a little damaged, so I thought of buying her another one, so I w...; wgsxsm Talking

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components