IDT71T75602S166PFG datasheet, PDF

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IDT71T75602S166PFG: DescriptionZBT SRAM, 512KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP-100; Categorystorage storage; File Size392KB，23 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT71T75602S166PFG Overview

ZBT SRAM, 512KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP-100

IDT71T75602S166PFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LQFP, QFP100,.63X.87
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	18874368 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.04 A
Minimum standby current	2.38 V
Maximum slew rate	0.245 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

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512K x 36, 1M x 18

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

• 512K x 36, 1M x 18 memory configurations

• Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

• ZBT

Feature - No dead cycles between write and read

cycles

• Internally synchronized output buffer enable eliminates the

need to control

• Single R/W (READ/WRITE) control pin

• Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

• 4-word burst capability (interleaved or linear)

• Individual byte write (BW

) control (May tie active)

• Three chip enables for simple depth expansion

• 2.5V power supply (±5%)

• 2.5V I/O Supply (V

DDQ

)

• Power down controlled by ZZ input

• Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

• Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

IDT71T75602

IDT71T75802

Features

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit

(18 Megabit) synchronous SRAMs. They are designed to eliminate dead

bus cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT

, or Zero

Bus Turnaround.

Address and control signals are applied to the SRAM during one

clock cycle, and two cycles later the associated data cycle occurs, be it

read or write.

The IDT71T75602/802 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable

CEN

pin allows operation of the IDT71T75602/802

to be suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the

user to deselect the device when desired. If any one of these three is not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

Description

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Input

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

N/A

Asynchronous

Synchronous

Static

APRIL 2012

DSC-5313/10

5313 tbl 01

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