USER’S GUIDE
LSI402ZX
Digital Signal Processor
February 2002
®
This document is preliminary. As such, it contains data derived from functional
simulations and performance estimates. LSI Logic has not verified either the
functional descriptions, or the electrical and mechanical specifications using
production parts.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB15-000153-03, Fourth Edition (February 2002)
This document describes LSI Logic Corporation’s LSI402ZX and will remain the
official reference source for all revisions/releases of this product until rescinded
by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright © 1999–2002 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, ZSP, and G12 are trademarks or registered
trademarks of LSI Logic Corporation. All other brand and product names may be
trademarks of their respective companies.
GL
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html
ii
Preface
This book is the primary reference and User’s Guide for the LSI402ZX
digital signal processor. It contains a complete functional description for
the product and includes complete physical and electrical specifications
for the LSI402ZX.
Audience
This document assumes that you have some familiarity with digital signal
processors and related support devices. The people who benefit from
this book are:
•
•
Organization
Engineers and managers who are evaluating the DSP for possible
use in a system
Engineers who are designing the DSP into a system
This document has the following chapters:
•
•
•
•
•
Chapter 1,
Introduction,
introduces the LSI402ZX and gives a brief
overview of the processor.
Chapter 2,
Hardware Architecture,
describes the functional blocks
that constitute the LSI402ZX.
Chapter 3,
Programmer’s Model,
describes the memory
architecture and registers.
Chapter 4,
Signal Descriptions,
describes the external LSI402ZX
interface.
Chapter 5,
Interrupts and Traps,
describes interrupt and exception
handling.
Preface
iii
•
•
Chapter 6,
Operation,
provides functional waveforms for the
LSI402ZX.
Chapter 7,
Specifications,
provides mechanical and electrical
specifications for the LSI402ZX.
Related Publications
The following documents are available from LSI Logic Corporation:
EB402 Evaluation Board User’s Guide,
Document No. DB15-0000143-01
EB402 Evaluation Board Getting Started,
Document No.
DB06-000264-02
ZSP™ SDK Software Developers Kit User’s Guide,
Document No.
DB15-000126-05
ZSP400 Digital Signal Processor Architecture Technical Manual,
Document No. DB14-000121-03
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is
italicized.
The word
assert
means to drive a signal true or active. The word
deassert
means to drive a signal false or inactive. Signals that are active
LOW end in an “N.”
To
set
a bit in a register means to write a one to the bit. To
clear
a bit
means to write a zero to the bit.
Hexadecimal numbers are indicated by the prefix “0x”—for example,
0x32CF. Binary numbers are indicated by the prefix “0b”—for example,
0b0011.0010.1100.1111.
iv
Preface
Contents
Chapter 1
Introduction
1.1
Description
1.2
Features
Hardware Architecture
2.1
Architecture Overview
2.2
Instruction Unit (IU)
2.3
Data Unit (DU)
2.3.1
Circular Buffering
2.3.2
Reverse Carry Addressing
2.4
Pipeline Control Unit (PCU)
2.5
Multiply Accumulate Units (MACs)
2.6
Arithmetic Logic Units (ALUs)
2.7
Register Files
2.7.1
Operand and Shadow Registers
2.7.2
Control Registers
2.8
Boot ROM
2.8.1
Boot Sequence
2.8.2
Diagnostic Self-Tests
2.8.3
Setup and Idle
2.8.4
Code Download Utility
2.8.5
Register Contents after Boot ROM Execution
2.9
Memory
2.10 DMA Controller Operation
2.10.1 Non-Indexed DMA Transfers
2.10.2 Indexed DMA Transfers
2.10.3 DMA Channel Priority
2.10.4 DMA Memory Map
2.10.5 DMA Data Coherency
1-1
1-3
Chapter 2
2-2
2-4
2-4
2-5
2-6
2-7
2-8
2-9
2-9
2-10
2-10
2-11
2-12
2-12
2-15
2-16
2-18
2-19
2-20
2-22
2-26
2-30
2-31
2-32
Contents
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