K4T2G044QA
K4T2G084QA
2Gb DDR2 SDRAM
2Gb A-die DDR2 SDRAM Specification
68FBGA with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.3 December 2008
K4T2G044QA
K4T2G084QA
2Gb DDR2 SDRAM
Table of Contents
1.0 Ordering Information ...................................................................................................................4
2.0 Key Features ................................................................................................................................4
3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................5
3.1 x4 package pinout (Top View) : 68ball FBGA Package
3.2 x8 package pinout (Top View) : 68ball FBGA Package
3.3 FBGA Package Dimension(x4/x8)
.......................................................................5
.......................................................................6
...................................................................................................7
4.0 Input/Output Functional Description .........................................................................................8
5.0 DDR2 SDRAM Addressing ..........................................................................................................9
6.0 Absolute Maximum DC Ratings ................................................................................................10
7.0 AC & DC Operating Conditions ................................................................................................10
7.1 Recommended DC Operating Conditions (SSTL - 1.8)
7.2 Operating Temperature Condition
7.3 Input DC Logic Level
7.4 Input AC Logic Level
.....................................................................10
................................................................................................ 11
.................................................................................................................. 11
.................................................................................................................. 11
............................................................................................................ 11
...................................................................................................12
................................................................................................12
7.5 AC Input Test Conditions
7.6 Differential input AC logic Level
7.7 Differential AC output parameters
8.0 ODT DC electrical characteristics .............................................................................................12
9.0 OCD default characteristics ......................................................................................................14
10.0 IDD Specification Parameters and Test Conditions .............................................................15
11.0 DDR2 SDRAM IDD Spec Table ................................................................................................16
12.0 Input/Output capacitance ........................................................................................................17
13.0 Electrical Characteristics & AC Timing for DDR2-800/667 ...................................................17
13.1 Refresh Parameters by Device Density
......................................................................................17
............................................17
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
13.3 Timing Parameters by Speed Grade
..........................................................................................18
14.0 General notes, which may apply for all AC parameters .......................................................20
15.0 Specific Notes for dedicated AC parameters ........................................................................ 22
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Rev. 1.3 December 2008
K4T2G044QA
K4T2G084QA
2Gb DDR2 SDRAM
Year
2008
2008
2008
2008
- Initial release
- Updated AC timing table with the JEDEC update(JESD79-2E)
- Erased the product of 800Mbps CL5 speed, and added 533Mbps CL4 product
- Updated AC/DC operating condition with the JEDEC update(JESD79-2E)
History
Revision History
Revision
1.0
1.1
1.2
1.3
Month
March
July
September
December
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Rev. 1.3 December 2008
K4T2G044QA
K4T2G084QA
1.0 Ordering Information
Organization
512Mx4
256Mx8
DDR2-800 6-6-6
K4T2G044QA-HCF7
K4T2G084QA-HCF7
DDR2-667 5-5-5
K4T2G044QA-HCE6
K4T2G084QA-HCE6
2Gb DDR2 SDRAM
DDR2-533 4-4-4
K4T2G044QA-HCD5
K4T2G084QA-HCD5
Package
68 FBGA
68 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2. x4/x8 Package - including 8 dummy balls.
3. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
2.0 Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-800 6-6-6
6
15
15
60
DDR2-667 5-5-5
5
15
15
60
DDR2-533 4-4-4
4
15
15
60
Units
tCK
ns
ns
ns
• JEDEC standard V
DD
= 1.8V ± 0.1V Power Supply
• V
DDQ
= 1.8V ± 0.1V
• 267MHz f
CK
for 533Mb/sec/pin, 333MHz f
CK
for 667Mb/sec/
pin, 400MHz f
CK
for 800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2, 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
-50ohm ODT
-High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
CASE
85°C,
3.9us at 85°C < T
CASE
< 95
°C
•
Package: 68ball FBGA - 512Mx4/256Mx8
The 2Gb DDR2 SDRAM is organized as a 64Mbit x 4 I/Os x 8
banks or 32Mbit x 8 I/Os x 8banks device. This synchronous
device achieves high speed double-data-rate transfer rates of up
to 800Mb/sec/pin (DDR2-800) for general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 2Gb(x4) device receive 15/
11/3 addressing.
The 2Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V V
DDQ
.
The 2Gb DDR2 device is available in 68ball FBGAs(x4/x8).
Note : The functionality described and the timing specifications included in
this data sheet are for the DLL Enabled mode of operation.
• All of products are Lead-Free, Halogen-Free, and RoHS
compliant
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
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Rev. 1.3 December 2008
K4T2G044QA
K4T2G084QA
3.0 Package Pinout/Mechanical Dimension & Addressing
2Gb DDR2 SDRAM
3.1 x4 package pinout (Top View) : 68ball FBGA Package
(60balls + 8balls of dummy balls)
1
NC
2
NC
3
7
A
B
C
D
8
9
NC
NC
V
DD
NC
V
DDQ
NC
V
DDL
NC
V
SSQ
DQ1
V
SSQ
V
REF
CKE
V
SS
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
SSQ
DQS
V
DDQ
DQ2
V
SSDL
RAS
CAS
A2
A6
A11
NC
DQS
V
SSQ
DQ0
V
SSQ
CK
CK
CS
A0
A4
A8
A13
V
DDQ
NC
V
DDQ
NC
V
DD
ODT
DM
V
DDQ
DQ3
V
SS
WE
BA1
A1
A5
A9
A14
BA2
BA0
A10/AP
V
DD
V
SS
A3
A7
V
SS
V
DD
A12
NC
NC
W
NC
NC
Note :
1. Pin E3 has identical capacitance as pin E7.
2. V
DDL
and V
SSDL
are power and ground for the DLL.
Ball Locations (x4)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
: Populated Ball
+ : Depopulated Ball
Top View
(See the balls through the package)
2
3
4
5
6
7
8
9
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Rev. 1.3 December 2008
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