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PM5360-BI

Description
Clock Recovery Circuit, 1-Func, CMOS, PBGA500, 31 X 31 MM, 1.47 MM HEIGHT, UBGA-500
CategoryWireless rf/communication    Telecom circuit   
File Size36KB,2 Pages
ManufacturerPMC-Sierra Inc
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PM5360-BI Overview

Clock Recovery Circuit, 1-Func, CMOS, PBGA500, 31 X 31 MM, 1.47 MM HEIGHT, UBGA-500

PM5360-BI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerPMC-Sierra Inc
package instruction31 X 31 MM, 1.47 MM HEIGHT, UBGA-500
Reach Compliance Codecompliant
JESD-30 codeS-PBGA-B500
JESD-609 codee0
length31 mm
Humidity sensitivity level3
Number of functions1
Number of terminals500
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)225
Maximum seat height1.62 mm
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Telecom integrated circuit typesATM/SONET/SDH CLOCK RECOVERY CIRCUIT
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width31 mm
Released
PM5360
S/UNI MULTI 48
Multi-rate SATURN User Network Interface for 1x2488, 4x622, and 4x155
FEATURES
• Single chip ATM and POS User
Network Interface that supports
1x2488.32 Mbit/s or a combination of
up to 4x622.08 Mbit/s and
155.52 Mbit/s.
• Implements the ATM Forum User
Network Interface Specification and
the ATM physical layer for Broadband
ISDN according to CCITT
Recommendation I.432.
• Implements the Point-to-Point Protocol
(PPP) over SONET/SDH specification
according to RFC 2615(1619)/1662 of
the PPP Working Group of the Internet
Engineering Task Force (IETF).
• Processes a duplex bit-serial
2488.32 Mbit/s STS-48 (STM-16) data
stream with on-chip clock and data
recovery and clock synthesis. The
STS-48 (STM-16) stream may contain
an STS-48c (AU4-16c) or a
combination of STS-12c (AU-4-4c) and
STS-3c (AU-4).
• Processes up to four duplex bit-serial
622.08 Mbit/s STS-12 (STM-4) data
streams with on-chip clock and data
recovery and clock synthesis. Each
STS-12 (STM-4) may contain a single
STS-12c (AU-4-4c) or up to four
STS-3c (AU-4).
• Processes up to four duplex bit-serial
155.52 Mbit/s STS-3 (STM-1) data
streams with on-chip clock and data
recovery and clock synthesis. Each
STS-3 (STM-1) may contain a single
STS-3c (AU-4).
• Permits mixed OC-12 and OC-3 data
streams.
• Complies with Telcordia
GR-253-CORE jitter tolerance, jitter
transfer, and intrinsic jitter criteria.
• Provides termination for SONET
Section, Line, and Path overhead or
SDH Regenerator Section, Multiplexer
Section, and High Order Path
overhead.
• Provides cross bar functionality to
swap STS-12 and STS-3 clients
to/from different line-side interfaces.
• Provides support for automatic
protection switching via a 4-bit LVDS
777.6 MHz port.
• Provides cross bar functionality to
swap STS-12 and STS-3 lines and/or
clients to/from different APS interfaces.
• Provides UTOPIA Level 3 32-bit wide
System Interface (clocked up to
104 MHz) with parity support for ATM
applications.
• Provides SATURN® POS-PHY™
Level 3 (32-bit System Interface
(clocked up to 104 MHz) for Packet
over SONET (POS) or ATM
applications.
• Supports independent loop-timed
operation for each transmit serial
stream.
APSI_P/N[4:1]
BLOCK DIAGRAM
TTOH[4:1]
TTOHEN[4:1]
TTOHFP[4:1]
TTOHCLK[4:1]
SYSCLK
LINE_IF
Transmit
Section
Trace
Processor
(4)
Transmit
Path
Trace
Processor
(4)
APSIFP
LVDS I/f
(4)
Receive
APS
(4)
SONET/APS
PL3/UL3
TXD_P/N[1]
Transmit 2488 Mbps
Analog Circuitry
Transmit 622 Mbps
Analog Circuitry
X-Bar
STPA
TCA/PTPA
TADR[3:0]
TENB
TSX
TSOC/TSOP
TEOP
TDAT[31:0]
TPRTY
TMOD[1:0]
TERR
TFCLK
TXD_P/N[4:2]
Transmit
Line
Interface
Transmit
Regen/
Multiplexor
Processor
(4)
Transmit
Virtual
Container
Aligner
(4)
Transmit
Path
Processor
(4)
In
band
Alarm
(4)
PRBS
generator
/ monitor
(4)
Transmit
X-Bar
Transmit
channel
Assigner
(4)
Transmit
ATM/POS
processor
(4)
Transmit
FIFO
UTOPIA L3/
POS-PHY
L3
Transmit
Interface
REFCLK155_P/N
REFCLK77_P/N
Clock
Synthesis
Unit
SARC
Alarm Report
Controller (4)
PL3EN
Bit error
rate mon
(4)
Receive
Regen/
Multiplexor
Processor
(4)
Receive
Virtual
Container
Aligner
(4)
UTOPIA L3/
POS-PHY
L3
Receive
Interface
RADR[3:0]
RENB
RFCLK
STS48EN
Receive
Line
Interface
Receive
Path
Processor
(4)
Receive
X-Bar
Receive
channel
Assigner
(4)
Receive
ATM/POS
processor
(4)
Receive
FIFO
RDAT[31:0]
RCA/RVAL
RPRTY
RSX
RSOC/RSOP
REOP
RMOD[1:0]
RXD_P/N[4:2]
Receive 622 Mbps
Analog Circuitry
Receive 2488 Mbps
Analog Circuitry
RXD_P/N[1]
SD[4:1]
SD_TEST
Receive
Section
Trace
Processor
(4)
Receive
Path
Trace
Processor
(4)
X-Bar
Transmit
APS
(4)
LVDS I/f
(4)
RERR
Microprocessor
Interface
JTAG
Interface
RTOHFP[4:1]
RTOH[4:1]
RTOHCLK[4:1]
SALM[4:1]
RALM[4:1]
B3E[4:1]
TCK
TDI
TMS
TRSTB
D[15:0]
A[13:0]
WRB
RDB
ALE
CSB
RSTB
APSO_P/N[4:1]
PMC-2021539 (R4)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
APSOFP
RCLKO
INTB
© Copyright PMC-Sierra, Inc. 2003
TDO

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