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SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
D
D
D
D
D
D
D
D
D
D
D
Eight Line Receivers Meet or Exceed the
Requirements of ANSI TIA/EIA-644
Standard
Integrated 110-Ω Line Termination
Resistors on LVDT Products
Designed for Signaling Rates
†
Up To
630 Mbps
SN65 Version’s Bus-Terminal ESD Exceeds
15 kV
Operates From a Single 3.3-V Supply
Propagation Delay Time of 2.6 ns (Typ)
Output Skew 100 ps (Typ)
Part-To-Part Skew Is Less Than 1 ns
LVTTL Levels Are 5-V Tolerant
Open-Circuit Fail Safe
Flow-Through Pin Out
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
NOT RECOMMENDED FOR NEW DESIGNS
For Replacement Use ’LVDx388A
’LVDS388, ’LVDT388
DBT PACKAGE
(TOP VIEW)
description
The ‘LVDS388 and ‘LVDT388 (T designates
integrated termination) are eight differential line
receivers that implement the electrical character-
istics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3-V
supply rail. Any of the eight differential receivers
will provide a valid logical output state with a
+100-mV differential input voltage within the input
common-mode voltage range. The input
common-mode voltage range allows 1 V of
ground potential difference between two LVDS
nodes. Additionally, the high-speed switching of
LVDS signals always require the use of a line
impedance matching resistor at the receiving end
of the cable or transmission media. The LVDT
product eliminates this external resistor by
integrating it with the receiver.
A1A
A1B
A2A
A2B
NC
B1A
B1B
B2A
B2B
NC
C1A
C1B
C2A
C2B
NC
D1A
D1B
D2A
D2B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
V
CC
ENA
A1Y
A2Y
ENB
B1Y
B2Y
GND
V
CC
GND
C1Y
C2Y
ENC
D1Y
D2Y
END
V
CC
GND
logic diagram (positive logic)
’LVDx388
’LVDT388 ONLY
1A
1Y
1B
EN
2A
2B
(1/4 of ’LVDx388 shown)
2Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001, Texas Instruments Incorporated
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•
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1
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
description (continued)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100
Ω.
The transmission media may be printed-circuit board
traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the
low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. When used with its companion, 8-channel driver, the SN65LVDS389 over
150 million data transfers per second in single-edge clocked systems are possible with very little power. Note:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media,
the noise coupling to the environment, and other system characteristics.
The SN65LVDS388 and SN65LVDT388 is characterized for operation from –40°C to 85°C. The SN75LVDS388
and SN75LVDT388 is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
PART NUMBER
SN65LVDS388DBT
SN65LVDT388DBT
SN75LVDS388DBT
SN75LVDT388DBT
TEMPERATURE
RANGE
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
NUMBER OF
RECEIVERS
8
8
8
8
BUS-PIN ESD
15 kV
15 kV
4 kV
4 kV
Function Table
SNx5LVD388 and SNx5LVDT388
DIFFERENTIAL INPUT
A-B
VID
≥
100 mV
-100 mV < VID
≤
100 mV
VID
≤
-100 mV
X
Open
ENABLES
EN
H
H
H
L
H
OUTPUT
Y
H
?
L
Z
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
VCC
VCC
VCC
300 kΩ
300 kΩ
400
Ω
EN
Y Output
5
Ω
A Input
7V
7V
B Input
7V
300 kΩ
7V
110
Ω
’LVDT Devices Only
2
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•
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SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V
Voltage range:
Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V
Electrostatic discharge: (see Note 2)
SN65’ (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:15 kV, B: 700 V
SN75’ (A, B, and GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2, A:4 kV, B: 400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
DERATING FACTOR‡
ABOVE TA = 25°C
PACKAGE
TA
≤
25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
556 mW
DBT
1071 mW
8.5 mW/°C
688 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
recommended operating conditions
MIN
Supply voltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
Magnitude of differential input voltage,
V
ID
|V
Common-mode input voltage, VIC (see Figure 4)
SN75’
O erating
Operating free-air tem erature, TA
temperature
SN65’
Enables
Enables
0.1
ID
2
|
2.4
3
2
0.8
0.6
ID
*
|V2 |
NOM
3.3
MAX
3.6
UNIT
V
V
V
V
V
°C
°C
0
– 40
VCC – 0.8
70
85
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3
SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VIT+
VIT–
VOH
VOL
ICC
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
Low-level output voltage
Supply current
’LVDS
II
Input current (A or B inputs)
’LVDT
IID
IID
II(OFF)
II(OFF)
IIH
IIL
IOZ
CIN
Differential input current |IIA – IIB|
Differential input current (IIA – IIB)
Power-off input current (A or B inputs)
Power-off input current (A or B inputs)
High-level input current (enables)
Low-level input current (enables)
High-impedance
High impedance output current
Input capacitance, A or B input to GND
‘LVDS
‘LVDT
‘LVDS
‘LVDT
TEST CONDITIONS
See Figure 1 and Table 1
IOH = –8 mA
IOL = 8 mA
Enabled,
Disabled
VI = 0 V
VI = 2.4 V
VI = 0 V, other input open
VI = 2.4 V, other input open
VIA = 0 V,
VIA = 2.4 V,
VIA = 0.2 V,
VIA = 2.4 V,
VCC = 0 V,
VCC = 0 V,
VIH = 2 V
VIL = 0.8 V
VO = 0 V
VO = 3.6 V
VID = 0.4 sin 2.5E09 t V
VID = 0.4 sin 2.5E09 t V
5
88
132
VIB = 0.1 V,
VIB = 2.3 V
VIB = 0 V,
VIB = 2.2 V
VI = 2.4 V
VI = 2.4 V
1.5
12
–13
–1.2
–2.4
±2
2.2
±20
±40
10
10
±1
10
µA
mA
µA
µA
µA
µA
µA
pF
Ω
–3
–40
No load
MIN
–100
2.4
3
0.2
50
0.4
70
3
–20
µA
TYP†
MAX
100
UNIT
mV
mV
V
V
mA
mA
Z(t)
Termination impedance
† All typical values are at 25°C and with a 3.3-V supply.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
tPHL
tr
tf
tsk(p)
tsk(o)
tsk(pp)
tPZH
tPZL
tPHZ
tPLZ
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
Output signal fall time
Pulse skew (|tPHL – tPLH|)
Output skew‡
Part-to-part skew§
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
See Figure 3
7
7
7
7
See Figure 2
g
TEST CONDITIONS
MIN
1
1
500
500
TYP†
2.6
2.5
800
800
150
100
MAX
4
4
1200
1200
600
400
1
15
15
15
15
UNIT
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
† All typical values are at 25°C and with a 3.3-V supply.
‡ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together.
§ tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data
sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
4
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