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M5M5V216ART-55LI

Description
Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44
Categorystorage    storage   
File Size100KB,8 Pages
ManufacturerMitsubishi
Websitehttp://www.mitsubishielectric.com/semiconductors/
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M5M5V216ART-55LI Overview

Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44

M5M5V216ART-55LI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMitsubishi
Parts packaging codeTSOP2
package instructionTSOP2-R, TSOP44,.46,32
Contacts44
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time55 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G44
JESD-609 codee0
length18.41 mm
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals44
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2-R
Encapsulate equivalent codeTSOP44,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3/3.3 V
Certification statusNot Qualified
reverse pinoutYES
Maximum seat height1.2 mm
Minimum standby current2 V
Maximum slew rate0.06 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
revision-02, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V216A is a f amily of low v oltage 2-Mbit static RAMs
organized as 131,072-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
The M5M5V216A is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V216ATP, RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V216ATP (normal lead bend ty pe package)
, M5M5V216ART (rev erse lead bend ty pe package) , both ty pes
are v ery easy to design a printed circuit board.
From the point of operating temperature, the f amily is div ided into
three v ersions; "Standard", "W-v ersion", and "I-v ersion". Those are
summarized in the part name table below.
FEATURES
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S , BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
PART NAME TABLE
Version,
Operating
temperature
Part name
M5M5V216ATP , RT -55L
Power
Supply
2.7 ~ 3.6V
2.7 ~ 3.6V
Access
time
Stand-by current Icc
(PD)
, Vcc=3.0V
ty pical *
Ratings (max.)
25 C
---
40 C
---
25 C
---
1µA
40 C
---
3µA
70 C
20µA
8µA
max.
55ns(@ 2.7V) / 50ns (@3.3V)
70ns (@ 2.7V) / 65ns (@3.3V)
55ns(@ 2.7V) / 50ns (@3.3V)
70ns (@ 2.7V) / 65ns (@3.3V)
55ns(@ 2.7V) / 50ns (@3.3V)
Activ e
current
Icc1
(3.0V, ty p.)
85 C
---
---
45mA
(10MHz)
5mA
(1MHz)
Standard
0 ~ +70 C
M5M5V216ATP , RT -70L
M5M5V216ATP , RT -55H
M5M5V216ATP , RT -70H
M5M5V216ATP , RT -55LW
0.3µA 1µA
W-
v ersion
-20 ~ +85 C
M5M5V216ATP , RT -70LW
M5M5V216ATP , RT -55HW
M5M5V216ATP , RT -70HW
M5M5V216ATP , RT -55L I
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
70ns (@ 2.7V) / 65ns (@3.3V)
55ns(@ 2.7V) / 50ns (@3.3V)
70ns (@ 2.7V) / 65ns (@3.3V)
55ns(@ 2.7V) / 50ns (@3.3V)
70ns (@ 2.7V) / 65ns (@3.3V)
55ns(@ 2.7V) / 50ns (@3.3V)
70ns (@ 2.7V) / 65ns (@3.3V)
---
---
---
1µA
---
1µA
---
3µA
---
3µA
20µA 50µA
8µA
24µA
0.3µA 1µA
---
---
I-
v ersion
-40 ~ +85 C
M5M5V216ATP , RT -70L I
M5M5V216ATP , RT -55H I
M5M5V216ATP , RT -70H I
20µA 50µA
8µA
24µA
0.3µA 1µA
PIN CONFIGURATION
A4
A3
A2
A1
A0
S
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
* "ty pical" parameter is sampled, not 100% tested.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BC2
BC1
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
A5
A6
A7
OE
BC2
BC1
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
S
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
Pin
A0 ~ A16
S
W
OE
BC1
BC2
Vcc
GND
Function
Address input
Chip select input
Write control input
Output inable input
Lower By te (DQ1 ~ 8)
Upper By te(DQ9 ~ 16)
Power supply
Ground supply
DQ1 ~ DQ16 Data input / output
Outline: TP :
44P3W - H
RT : 44P3W - J
NC: No Connection
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