SL28442-2
Clock Generator for Intel
®
Alviso Chipset
Features
• Compliant to Intel
®
CK410M
• Supports Intel Pentium-M CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• SRC clocks independently stoppable through
CLKREQ#[A:B]
CPU
x2 / x3
SRC
x5/6/7
DOT96
x1
PCI
x6
REF
x2
SSCG USB_48
x1
x1
• 96 /100 MHz Spreadable differential clock.
• 33 MHz PCI clock
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin TSSOP package
Block Diagram
Pin Configuration
VDD_REF
REF
IREF
VDD_CPU
CPUT
CPUC
VDD_CPU
CPUT_ITP/SRCT7
CPUC_ITP/SRCC7
VDD_SRC
SRCT[1:5]
CPUC[1:5]
VDD_PCI
PCI
VDD_PCI
PCIF
PLL2
96MSS
VDD_48MHz
96_100_SSCT
96_100_SSCC
VDD_48MHz
DOT96T
DOT96C
VDD_48
USB
XIN
XOUT
PCI_STP#
CPU_STP#
CLKREQ[A:B]#
FS_[C:A]
14.318MHz
Crystal
PLL Reference
PLL1
CPU
Divider
Divider
PLL3
FIXED
VTTPWR_GD#/PD
Divider
VDD_REF
VSS_REF
PCI3
PCI4
PCI5
VSS_PCI
VDD_PCI
ITP_EN/PCIF0
**96_100_SEL/PCIF1
*VTTPWRGD#/PD
VDD_48
FS_A/48M_0
VSS_48
DOT96T
DOT96C
FS_B/TESTMODE
96_100_SSCT
96_100_SSCC
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
SRCC4_SATA
VDD_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2/SEL_CLKREQ**
PCI_STP#*
CPU_STP#*
FS_C_TEST_SE/REF0
REF1
VSSA2
XIN
XOUT
VDDA2
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPU2T_ITP/SRCT7
CPU2C_ITP/SRCC7
VDD_SRC_ITP
SRCT6/CLKREQA#*
SRCC6/CLKREQB#*
SRCT5
SRCC5
VSS_SRC
SL28442-2
56 pin TSSOP
SDATA
SCLK
I2C
Logic
* Internal pull-up
** Internal pull-down
Rev 1.2, July 3 , 2007
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 21
www.SpectraLinear.com
SL28442-2
Pin Definitions
Pin No.
1
2
33,32
Name
VDD_REF
VSS_REF
CLKREQA#/SRCT6,
CLKREQB#/SRCC6
Type
PWR
GND
3.3V power supply for output
Ground for outputs.
Description
I/O, PU
3.3V LVTTL input for enabling assigned SRC clock (active low) /100MHz
Serial Reference Clock.
Selectable through CLKREQA# defaults to enable/disable SRCT/C4,
CLKREQB# defaults to enable/disable SRCT/C5. Assignment can be changed
via SMBUS register Byte 8.
PWR
GND
3.3V power supply for outputs.
Ground for outputs.
7
6
3,4,5
8
VDD_PCI
VSS_PCI
PCI
ITP_EN/PCIF0
O, SE
33-MHz clock
I/O, SE
3.3V LVTTL input to enable SRC7 or CPU2_ITP/33MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
I/O,
33-MHz clock/3.3V-tolerant input for 96_100M frequency selection
PD,SE (sampled on the VTT_PWRGD# assertion).
1 = 100 MHz, 0 = 96 MHz
I, PU
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ.
After
VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for
asserting power down (active HIGH).
3.3V power supply for outputs.
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
3.3V-tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
9
PCIF1/96_100_SEL
10
VTT_PWRGD#/PD
11
12
13
14,15
16
VDD_48
FS_A/48_M0
VSS_48
DOT96T, DOT96C
FS_B/TEST_MODE
PWR
I/O
GND
I
O, DIF
Fixed 96-MHz clock output.
17,18
96_100_SSC
O,DIF
Differential 96-/100-MHz SS clock for flat-panel display
O, DIF
100-MHz Differential serial reference clocks.
PWR
PWR
3.3V power supply for outputs.
3.3V power supply for outputs.
19,20,22,23, SRCT/C
24,25,30,31
21,28
34
26,27
29
36,35
VDD_SRC
VDD_SRC_ITP
SRC4_SATAT,
SRC4_SATAC
VSS_SRC
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
VDDA
VSSA
IREF
VDD_CPU
VSS_CPU
SCLK
SDATA
VDDA2
O, DIF
Differential serial reference clock.
Recommended output for SATA.
GND
Ground for outputs.
O, DIF
Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
PWR
GND
I
PWR
GND
I
I/O
PWR
3.3V power supply for PLL.
Ground for PLL.
A precision resistor is attached to this pin,
which is connected to the internal
current reference.
3.3V power supply for outputs.
Ground for outputs.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
3.3V power supply for PLL2
37
38
39
42
45
46
47
48
40, 41,43,44 CPUT/C
O, DIF
Differential CPU clock outputs.
Rev 1.2, July 3 , 2007
Page 2 of 21
SL28442-2
Pin Definitions
(continued)
Pin No.
49
50
51
52
53
XOUT
XIN
VSSA2
REF1
FS_C_TEST_SEL/
REF0
Name
Type
O, SE
14.318-MHz crystal output.
I
GND
O
I/O
14.318-MHz crystal input.
Ground for PLL2.
Fixed 14.318 MHz clock output.
3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to greater than 1.8V when VTT_PWRGD# is asserted
LOW.
Refer to DC Electrical Specifications table for
V
IL_FS
,V
IH_FS
specifications.
3.3V LVTTL input for CPU_STP# active low.
3.3V LVTTL input for PCI_STP# active low.
Description
54
55
56
CPU_STP#
PCI_STP#
PCI2/SEL_CLKREQ
I, PU
I, PU
I/O, PD
3.3V-tolerant input for CLKREQ pin selection/fixed 33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = pins 32,33 function as clk request pins, 0 = pins 32,33 function as SRC outputs.
Table 1. Frequency Select Table FS_A, FS_B and FS_C
FS_C
1
0
0
0
FS_B
0
0
1
1
FS_A
1
1
1
0
CPU
100 MHz
66.6667 MHz
83.3333 MHz
71.4286 MHz
SRC
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
Frequency Select Pins (FS_A, FS_B, and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B, and FS_C input values. For all logic
levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B, and FS_C transitions will be ignored, except in
test mode.
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Start
Slave address – 7 bits
Description
Bit
1
8:2
Start
Slave address – 7 bits
Block Read Protocol
Description
Rev 1.2, July 3 , 2007
Page 3 of 21
SL28442-2
Table 3. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Control Registers
Byte 0: Control Register 0
Bit
7
6
@Pup
1
1
Name
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
SRC[T/C]6
Description
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
Rev 1.2, July 3 , 2007
Page 4 of 21
SL28442-2
Byte 0: Control Register 0
(continued)
Bit
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
Name
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
RESERVED
Description
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
0
Name
PCIF0
DOT_96T/C
USB_48
REF0
REF1
CPU[T/C]1
CPU[T/C]0
CPU
Description
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
Reserved
Reserved
Reserved
PCIF1
Description
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
7
6
@Pup
0
0
Name
SRC7
SRC6
Description
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Rev 1.2, July 3 , 2007
Page 5 of 21
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