K4E660412D-TC500 datasheet, PDF

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K4E660412D-TC500: DescriptionEDO DRAM, 16MX4, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32; Categorystorage storage; File Size416KB，21 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4E660412D-TC500 Overview

EDO DRAM, 16MX4, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32

K4E660412D-TC500 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FAST PAGE WITH EDO
Maximum access time	50 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
JESD-30 code	R-PDSO-G32
length	20.95 mm
memory density	67108864 bit
Memory IC Type	EDO DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	32
word count	16777216 words
character code	16000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	10.16 mm

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K4E660412D,K4E640412D

CMOS DRAM

16M x 4bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random

access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-

mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden

refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 EDO Mode DRAM family is fabricated

using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

• Part Identification

- K4E660412D-JC/L(3.3V, 8K Ref., SOJ)

- K4E640412D-JC/L(3.3V, 4K Ref., SOJ)

- K4E660412D-TC/L(3.3V, 8K Ref., TSOP)

- K4E640412D-TC/L(3.3V, 4K Ref., TSOP)

• Extended Data Out Mode operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• Fast parallel test mode capability

• LVTTL(3.3V) compatible inputs and outputs

•

Active Power Dissipation

Unit : mW

Speed

-45

-50

-60

•

Refresh Cycles

Part

NO.

K4E660412D*

K4E640412D

Refresh

cycle

Refresh time

Normal

64ms

L-ver

128ms

RAS

CAS

Control

Clocks

VBB Generator

Vcc

Vss

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic SOJ and TSOP(II) packages

• +3.3V±0.3V power supply

432

396

360

324

288

252

FUNCTIONAL BLOCK DIAGRAM

Refresh Control

Refresh Counter

Memory Array

16,777,216 x 4

Cells

Sense Amps & I/O

* Access mode & RAS only refresh mode

: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

•

Performance Range

Speed

-45

-50

-60

Refresh Timer

Row Decoder

Data in

Buffer

DQ0

DQ3

Data out

Buffer

RAC

45ns

50ns

60ns

CAC

12ns

13ns

15ns

74ns

84ns

104ns

HPC

17ns

20ns

25ns

A0~A12

(A0~A11)*1

A0~A10

(A0~A11)*1

Row Address Buffer

Col. Address Buffer

Column Decoder

Note) *1 : 4K Refresh

SAMSUNG ELECTRONICS CO., LTD.

reserves the right to

change products and specifications without notice.

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