CA3140, CA3140A
Data Sheet
September 1998
File Number 957.4
4.5MHz, BiMOS Operational Amplifier with
MOSFET Input/Bipolar Output
The CA3140A and CA3140 are integrated circuit operational
amplifiers that combine the advantages of high voltage PMOS
transistors with high voltage bipolar transistors on a single
monolithic chip.
The CA3140A and CA3140 BiMOS operational amplifiers
feature gate protected MOSFET (PMOS) transistors in the
input circuit to provide very high input impedance, very low
input current, and high speed performance. The CA3140A
and CA3140 operate at supply voltage from 4V to 36V (either
single or dual supply). These operational amplifiers are
internally phase compensated to achieve stable operation in
unity gain follower operation, and additionally, have access
terminal for a supplementary external capacitor if additional
frequency roll-off is desired. Terminals are also provided for
use in applications requiring input offset voltage nulling. The
use of PMOS field effect transistors in the input stage results
in common mode input voltage capability down to 0.5V below
the negative supply terminal, an important attribute for single
supply applications. The output stage uses bipolar transistors
and includes built-in protection against damage from load
terminal short circuiting to either supply rail or to ground.
The CA3140 Series has the same 8-lead pinout used for the
“741” and other industry standard op amps. The CA3140A and
CA3140 are intended for operation at supply voltages up to 36V
(±18V).
Features
• MOSFET Input Stage
- Very High Input Impedance (Z
IN
) -1.5TΩ (Typ)
- Very Low Input Current (I
l
) -10pA (Typ) at
±15V
- Wide Common Mode Input Voltage Range (V
lCR
) - Can be
Swung 0.5V Below Negative Supply Voltage Rail
- Output Swing Complements Input Common Mode
Range
• Directly Replaces Industry Type 741 in Most
Applications
Applications
• Ground-Referenced Single Supply Amplifiers in Automo-
bile and Portable Instrumentation
• Sample and Hold Amplifiers
• Long Duration Timers/Multivibrators
(µseconds-Minutes-Hours)
• Photocurrent Instrumentation
• Peak Detectors
• Active Filters
• Comparators
• Interface in 5V TTL Systems and Other Low
Supply Voltage Systems
• All Standard Operational Amplifier Applications
• Function Generators
• Tone Controls
• Power Supplies
• Portable Instruments
• Intrusion Alarm Systems
Ordering Information
PART NUMBER
(BRAND)
CA3140AE
CA3140AM
(3140A)
CA3140AS
CA3140AT
CA3140E
CA3140M
(3140)
CA3140M96
(3140)
CA3140T
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
8 Ld PDIP
8 Ld SOIC
8 Pin Metal Can
8 Pin Metal Can
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC Tape
and Reel
8 Pin Metal Can
T8.C
PKG.
NO.
E8.3
M8.15
T8.C
T8.C
E8.3
M8.15
Pinouts
CA3140 (METAL CAN)
TOP VIEW
TAB
8
OFFSET
NULL
INV. 2
INPUT
NON-INV.
INPUT
3
1
7
V+
6 OUTPUT
STROBE
-
+
5 OFFSET
NULL
4
V- AND CASE
CA3140 (PDIP, SOIC)
TOP VIEW
OFFSET
NULL
INV. INPUT
NON-INV.
INPUT
V-
1
2
3
4
8
STROBE
V+
OUTPUT
OFFSET
NULL
-
+
7
6
5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
©
Intersil Corporation 1999
CA3140, CA3140A
Absolute Maximum Ratings
DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) To (V- -0.5V)
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . . Indefinite
.
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
Metal Can Package . . . . . . . . . . . . . . .
170
85
Maximum Junction Temperature (Metal Can Package). . . . . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications
PARAMETER
V
SUPPLY
=
±15V,
T
A
= 25
o
C
TYPICAL VALUES
SYMBOL
TEST CONDITIONS
Typical Value of Resistor
Between Terminals 4 and 5 or 4 and 1 to
Adjust Max V
IO
R
I
C
I
R
O
e
N
e
N
BW = 140kHz, R
S
= 1MΩ
R
S
= 100Ω
f = 1kHz
f = 10kHz
CA3140
4.7
CA3140A
18
UNITS
kΩ
Input Offset Voltage Adjustment Resistor
Input Resistance
Input Capacitance
Output Resistance
Equivalent Wideband Input Noise Voltage
(See Figure 27)
Equivalent Input Noise Voltage (See Figure 35)
1.5
4
60
48
40
12
40
18
4.5
9
220
1.5
4
60
48
40
12
40
18
4.5
9
220
0.08
10
4.5
1.4
TΩ
pF
Ω
µV
nV/√Hz
nV/√Hz
mA
mA
MHz
V/µs
µA
µs
%
µs
µs
Short Circuit Current to Opposite Supply
I
OM
+
I
OM
-
Source
Sink
Gain-Bandwidth Product, (See Figures 6, 30)
Slew Rate, (See Figure 31)
Sink Current From Terminal 8 To Terminal 4 to
Swing Output Low
Transient Response (See Figure 28)
f
T
SR
t
r
OS
R
L
= 2kΩ
C
L
= 100pF
R
L
= 2kΩ
C
L
= 100pF
Voltage Follower
Rise Time
Overshoot
To 1mV
To 10mV
0.08
10
4.5
1.4
Settling Time at 10V
P-P
, (See Figure 5)
t
S
Electrical Specifications
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Large Signal Voltage Gain (Note 3)
(See Figures 6, 29)
For Equipment Design, at V
SUPPLY
=
±15V,
T
A
= 25
o
C, Unless Otherwise Specified
CA3140
SYMBOL
|V
IO
|
|I
IO
|
I
I
A
OL
MIN
-
-
-
20
86
TYP
5
0.5
10
100
100
MAX
15
30
50
-
-
MIN
-
-
-
20
86
CA3140A
TYP
2
0.5
10
100
100
MAX
5
20
40
-
-
UNITS
mV
pA
pA
kV/V
dB
2
CA3140, CA3140A
Application Information
Circuit Description
As shown in the block diagram, the input terminals may be
operated down to 0.5V below the negative supply rail. Two
class A amplifier stages provide the voltage gain, and a
unique class AB amplifier stage provides the current gain
necessary to drive low-impedance loads.
A biasing circuit provides control of cascoded constant current
flow circuits in the first and second stages. The CA3140
includes an on chip phase compensating capacitor that is
sufficient for the unity gain voltage follower configuration.
When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, transistor Q
16
is the current
sinking element. Transistor Q
16
is mirror connected to D
6
, R
7
,
with current fed by way of Q
21
, R
12
, and Q
20
. Transistor Q
20
, in
turn, is biased by current flow through R
13
, zener D
8
, and R
14
.
The dynamic current sink is controlled by voltage level sensing.
For purposes of explanation, it is assumed that output Terminal
6 is quiescently established at the potential midpoint between
the V+ and V- supply rails. When output current sinking mode
operation is required, the collector potential of transistor Q
13
is
driven below its quiescent level, thereby causing Q
17
, Q
18
to
decrease the output voltage at Terminal 6. Thus, the gate
terminal of PMOS transistor Q
21
is displaced toward the V- bus,
thereby reducing the channel resistance of Q
21
. As a
consequence, there is an incremental increase in current flow
through Q
20
, R
12
, Q
21
, D
6
, R
7
, and the base of Q
16
. As a
result, Q
16
sinks current from Terminal 6 in direct response to
the incremental change in output voltage caused by Q
18
. This
sink current flows regardless of load; any excess current is
internally supplied by the emitter-follower Q
18
. Short circuit
protection of the output circuit is provided by Q
19
, which is
driven into conduction by the high voltage drop developed
across R
11
under output short circuit conditions. Under these
conditions, the collector of Q
19
diverts current from Q
4
so as to
reduce the base current drive from Q
17
, thereby limiting current
flow in Q
18
to the short circuited load terminal.
Input Stage
The schematic diagram consists of a differential input stage
using PMOS field-effect transistors (Q
9
, Q
10
) working into a
mirror pair of bipolar transistors (Q
11
, Q
12
) functioning as load
resistors together with resistors R
2
through R
5
. The mirror pair
transistors also function as a differential-to-single-ended
converter to provide base current drive to the second stage
bipolar transistor (Q
13
). Offset nulling, when desired, can be
effected with a 10kΩ potentiometer connected across
Terminals 1 and 5 and with its slider arm connected to Terminal
4. Cascode-connected bipolar transistors Q
2
, Q
5
are the
constant current source for the input stage. The base biasing
circuit for the constant current source is described
subsequently. The small diodes D
3
, D
4
, D
5
provide gate oxide
protection against high voltage transients, e.g., static electricity.
Bias Circuit
Quiescent current in all stages (except the dynamic current
sink) of the CA3140 is dependent upon bias current flow in R
1
.
The function of the bias circuit is to establish and maintain
constant current flow through D
1
, Q
6
, Q
8
and D
2
. D
1
is a diode
connected transistor mirror connected in parallel with the base
emitter junctions of Q
1
, Q
2
, and Q
3
. D
1
may be considered as a
current sampling diode that senses the emitter current of Q
6
and automatically adjusts the base current of Q
6
(via Q
1
) to
maintain a constant current through Q
6
, Q
8
, D
2
. The base
currents in Q
2
, Q
3
are also determined by constant current flow
D
1
. Furthermore, current in diode connected transistor Q
2
establishes the currents in transistors Q
14
and Q
15
.
Second Stage
Most of the voltage gain in the CA3140 is provided by the
second amplifier stage, consisting of bipolar transistor Q
13
and its cascode connected load resistance provided by
bipolar transistors Q
3
, Q
4
. On-chip phase compensation,
sufficient for a majority of the applications is provided by C
1
.
Additional Miller-Effect compensation (roll off) can be
accomplished, when desired, by simply connecting a small
capacitor between Terminals 1 and 8. Terminal 8 is also
used to strobe the output stage into quiescence. When
terminal 8 is tied to the negative supply rail (Terminal 4) by
mechanical or electrical means, the output Terminal 6
swings low, i.e., approximately to Terminal 4 potential.
Typical Applications
Wide dynamic range of input and output characteristics with
the most desirable high input impedance characteristics is
achieved in the CA3140 by the use of an unique design based
upon the PMOS Bipolar process. Input common mode voltage
range and output swing capabilities are complementary,
allowing operation with the single supply down to 4V.
The wide dynamic range of these parameters also means
that this device is suitable for many single supply
applications, such as, for example, where one input is driven
below the potential of Terminal 4 and the phase sense of the
output signal must be maintained – a most important
consideration in comparator applications.
Output Stage
The CA3140 Series circuits employ a broad band output stage
that can sink loads to the negative supply to complement the
capability of the PMOS input stage when operating near the
negative rail. Quiescent current in the emitter-follower cascade
circuit (Q
17
, Q
18
) is established by transistors (Q
14
, Q
15
)
whose base currents are “mirrored” to current flowing through
diode D
2
in the bias circuit section. When the CA3140 is
operating such that output Terminal 6 is sourcing current,
transistor Q
18
functions as an emitter-follower to source current
from the V+ bus (Terminal 7), via D
7
, R
9
, and R
11
. Under these
conditions, the collector potential of Q
13
is sufficiently high to
permit the necessary flow of base current to emitter follower
Q
17
which, in turn, drives Q
18
.
5
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