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PHB45NQ10T
N-channel TrenchMOS standard level FET
Rev. 02 — 8 July 2010
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Higher operating power due to low
thermal resistance
Low conduction losses due to low
on-state resistance
Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
DC-to-DC convertors
Switched-mode power supplies
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
drain-source
on-state
resistance
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
mb
= 25 °C; V
GS
= 10 V
T
mb
= 25 °C
Min
-
-
-
Typ
-
-
-
Max Unit
100
47
150
V
A
W
Static characteristics
R
DSon
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C
-
22
25
mΩ
Dynamic characteristics
Q
GD
gate-drain charge V
GS
= 10 V; I
D
= 45 A;
V
DS
= 80 V; T
j
= 25 °C
-
25
-
nC
NXP Semiconductors
PHB45NQ10T
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
[1]
source
mounting base; connected to
drain
2
1
3
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
SOT404 (D2PAK)
[1]
It is not possible to make connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
PHB45NQ10T
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
PHB45NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 8 July 2010
2 of 12
NXP Semiconductors
PHB45NQ10T
N-channel TrenchMOS standard level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
non-repetitive avalanche
current
T
mb
= 25 °C
pulsed; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 40 A;
V
sup
≤
25 V; unclamped; t
p
= 100 µs;
R
GS
= 50
Ω
V
sup
≤
25 V; V
GS
= 10 V; T
j(init)
= 25 °C;
R
GS
= 50
Ω;
unclamped
V
GS
= 10 V; T
mb
= 100 °C
V
GS
= 10 V; T
mb
= 25 °C
pulsed; T
mb
= 25 °C
T
mb
= 25 °C
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≤
175 °C; T
j
≥
25 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
100
100
20
33
47
188
150
175
175
47
188
260
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
I
AS
-
47
A
100
P
der
(%)
80
014aab202
100
I
D
(%)
80
014aab203
60
60
40
40
20
20
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig 2.
Normalized continuous drain current as a
function of mounting base temperature
PHB45NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 8 July 2010
3 of 12
NXP Semiconductors
PHB45NQ10T
N-channel TrenchMOS standard level FET
10
3
I
DM
(A)
10
2
R
DSon
= V
DS
/I
D
014aab204
10
2
014aab216
tp = 10
μs
100
μs
l
AS
(A)
25
°C
10
DC
1
1 ms
10 ms
100 ms
10
T
j
prior to avalanche = 150
°C
10
−1
1
10
10
2
V
DS
(V)
10
3
1
10
−3
10
−2
10
−1
1
t
AV
(ms)
10
T
mb
= 25 °C; I
DM
is single pulse
Fig 3.
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
Fig 4.
Single-shot avalanche rating; avalanche
current as a function of avalanche period
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
mounted on printed-circuit board ;
minimum footprint
Conditions
Min
-
Typ
-
Max
1
Unit
K/W
R
th(j-a)
-
50
-
K/W
1
Z
th j-mb
(K/W)
10
−1
δ
= 0.5
014aab205
0.2
0.1
0.05
0.02
P
δ
=
t
p
T
10
−2
single pulse
t
p
t
T
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHB45NQ10T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 8 July 2010
4 of 12
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