MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by PZT2222AT1/D
NPN Silicon Planar
Epitaxial Transistor
This NPN Silicon Epitaxial transistor is designed for use in linear and switching
applications. The device is housed in the SOT-223 package which is designed for
medium power surface mount applications.
•
PNP Complement is PZT2907AT1
•
The SOT-223 package can be soldered using wave or reflow.
•
SOT-223 package ensures level mounting, resulting in improved thermal
conduction, and allows visual inspection of soldered joints. The formed
leads absorb thermal stress during soldering, eliminating the possibility of
damage to the die.
•
Available in 12 mm tape and reel
Use PZT2222AT1 to order the 7 inch/1000 unit reel.
Use PZT2222AT3 to order the 13 inch/4000 unit reel.
BASE
1
3
EMITTER
COLLECTOR
2, 4
PZT2222AT1
Motorola Preferred Device
SOT-223 PACKAGE
NPN SILICON
TRANSISTOR
SURFACE MOUNT
4
1
2
3
CASE 318E-04, STYLE 1
TO-261AA
MAXIMUM RATINGS
Rating
Collector-Emitter Voltage
Collector-Base Voltage
Emitter-Base Voltage (Open Collector)
Collector Current
Total Power Dissipation up to TA = 25°C(1)
Storage Temperature Range°
Junction Temperature°
Symbol
VCEO
VCBO
VEBO
IC
PD
Tstg
TJ
Value
40
75
6.0
600
1.5
– 65 to +150
150
Unit
Vdc
Vdc
Vdc
mAdc
Watts
°C
°C
THERMAL CHARACTERISTICS
Thermal Resistance from Junction to Ambient
Lead Temperature for Soldering, 0.0625″ from case
Time in Solder Bath
R
θJA
TL
83.3
260
10
°C/W
°C
Sec
DEVICE MARKING
P1F
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Collector-Emitter Breakdown Voltage (IC = 10 mAdc, IB = 0)
Collector-Base Breakdown Voltage (IC = 10
µAdc,
IE = 0)
Emitter-Base Breakdown Voltage (IE = 10
µAdc,
IC = 0)
Base-Emitter Cutoff Current (VCE = 60 Vdc, VBE = – 3.0 Vdc)
Collector-Emitter Cutoff Current (VCE = 60 Vdc, VBE = – 3.0 Vdc)
Emitter-Base Cutoff Current (VEB = 3.0 Vdc, IC = 0)
Thermal Clad is a trademark of the Bergquist Company
Preferred
devices are Motorola recommended choices for future use and best overall value.
V(BR)CEO
V(BR)CBO
V(BR)EBO
IBEX
ICEX
IEBO
40
°75°
6.0
—
—
—
—
°—°
—
20
10
100
Vdc
Vdc
Vdc
nAdc
nAdc
nAdc
1. Device mounted on an epoxy printed circuit board 1.575 inches x 1.575 inches x 0.059 inches; mounting pad for the collector lead min. 0.93 inches2.
REV 2
©
Motorola, Inc. 1996
Motorola Small–Signal Transistors, FETs and Diodes Device Data
1
PZT2222AT1
ELECTRICAL CHARACTERISTICS — continued
(TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS (continued)
Collector-Base Cutoff Current
(VCB = 60 Vdc, IE = 0)
(VCB = 60 Vdc, IE = 0, TA = 125°C)
ICBO
—
—
10
10
nAdc
µAdc
ON CHARACTERISTICS
DC Current Gain
(IC = 0.1 mAdc, VCE = 10 Vdc)
(IC = 1.0 mAdc, VCE = 10 Vdc)
(IC = 10 mAdc, VCE = 10 Vdc)
(IC = 10 mAdc, VCE = 10 Vdc, TA = – 55°C)
(IC = 150 mAdc, VCE = 10 Vdc)
(IC = 150 mAdc, VCE = 1.0 Vdc)
(IC = 500 mAdc, VCE = 10 Vdc)
Collector-Emitter Saturation Voltages
(IC = 150 mAdc, IB = 15 mAdc)
(IC = 500 mAdc, IB = 50 mAdc)
Base-Emitter Saturation Voltages
(IC = 150 mAdc, IB = 15 mAdc)
(IC = 500 mAdc, IB = 50 mAdc)
Input Impedance°
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz)
Voltage Feedback Ratio
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz)
Small-Signal Current Gain
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz)
Output Admittance°
(VCE = 10 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
(VCE = 10 Vdc, IC = 10 mAdc, f = 1.0 kHz)
Noise Figure (VCE = 10 Vdc, IC = 100
µAdc,
f = 1.0 kHz)
hFE
35
50
70
35
100
50
40
VCE(sat)
—
—
VBE(sat)
0.6
—
°h
ie
°
2.0
0.25
hre
—
—
hfe
50
75
°h
oe
°
5.0
25
F
—
35
200
4.0
dB
300
375
µmhos
8.0
1.25
—
8.0x10-4
4.0x10-4
—
1.2
2.0
kΩ
0.3
1.0
Vdc
—
—
—
—
300
—
—
Vdc
—
DYNAMIC CHARACTERISTICS
Current-Gain — Bandwidth Product
(IC = 20 mAdc, VCE = 20 Vdc, f = 100 MHz)
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz)
Input Capacitance
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz)
fT
Cc
Ce
300
—
—
—
8.0
25
MHz
pF
pF
SWITCHING TIMES
(TA = 25°C)
Delay Time
Rise Time
Storage Time
Fall Time
(VCC = 30 Vdc, IC = 150 mAdc,
IB(on) = 15 mAdc, VEB(off) = 0.5 Vdc)
Figure 1
(VCC = 30 Vdc, IC = 150 mAdc,
IB(on) = IB(off) = 15 mAdc)
Figure 2
td
tr
ts
tf
—
—
—
—
10
25
225
60
ns
ns
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
PZT2222AT1
Vi
90%
R1
0
tr
tp
10%
Vi
R2
Vo
D.U.T.
VCC
Figure 1. Input Waveform and Test Circuit for Determining Delay Time and Rise Time
Vi = – 0.5 V to +9.9 V, VCC = +30 V, R1 = 619
Ω,
R2 = 200
Ω.
PULSE GENERATOR:
PULSE DURATION
RISE TIME
DUTY FACTOR
tp
≤
tr
≤
δ
=
200 ns
2 ns
0.02
OSCILLOSCOPE:
INPUT IMPEDANCE
INPUT CAPACITANCE
RISE TIME
Zi
Ci
tr
> 100 kΩ
<
12 pF
<
5 ns
Vi
+16.2 V
VCC
R2
D.U.T.
R3
Vo
OSCILLOSCOPE
R4
tf
100
µs
VBB
R1
0
TIME
Vi
D1
– 13.8 V
Figure 2. Input Waveform and Test Circuit for Determining Storage Time and Fall Time
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3
PZT2222AT1
INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
0.15
3.8
0.079
2.0
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.091
2.3
0.079
2.0
0.059
1.5
0.059
1.5
0.091
2.3
0.248
6.3
0.059
1.5
inches
mm
SOT-223
SOT-223 POWER DISSIPATION
The power dissipation of the SOT-223 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by T J(max), the maximum rated junction temperature of the
die, R
θJA
, the thermal resistance from the device junction to
ambient, and the operating temperature, TA . Using the
values provided on the data sheet for the SOT-223 package,
PD can be calculated as follows:
PD =
TJ(max) – TA
R
θJA
dissipation can almost be doubled with this method, area is
taken up on the printed circuit board which can defeat the
purpose of using surface mount technology. A graph of R
θJA
versus collector pad area is shown in Figure 3.
160
R JA , Thermal Resistance, Junction
to Ambient ( C/W)
Board Material = 0.0625″
G-10/FR-4, 2 oz Copper
0.8 Watts
TA = 25°C
140
°
120
1.25 Watts*
1.5 Watts
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 1.5 watts.
PD = 150°C – 25°C = 1.5 watts
83.3°C/W
The 83.3°C/W for the SOT-223 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.5 watts. There are
other alternatives to achieving higher power dissipation from
the SOT-223 package. One is to increase the area of the
collector pad. By increasing the area of the collector pad, the
power dissipation can be increased. Although the power
100
*Mounted on the DPAK footprint
0.2
0.4
0.6
A, Area (square inches)
0.8
1.0
θ
80
0.0
Figure 3. Thermal Resistance versus Collector
Pad Area for the SOT-223 Package (Typical)
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad™. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
PZT2222AT1
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass
or stainless steel with a typical thickness of 0.008 inches.
The stencil opening size for the SOT-223 package should be
the same as the pad size on the printed circuit board, i.e., a
1:1 registration.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•
Always preheat the device.
•
The delta temperature between the preheat and
soldering should be 100°C or less.*
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference should be a maximum of 10°C.
•
The soldering temperature and time should not exceed
260°C for more than 10 seconds.
•
When shifting from preheating to soldering, the
maximum temperature gradient should be 5°C or less.
•
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•
Mechanical stress or shock should not be applied during
cooling
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a
figure for belt speed. Taken together, these control settings
make up a heating “profile” for that particular circuit board.
On machines controlled by a computer, the computer
remembers these profiles from one operating session to the
next. Figure 4 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems but it is a good
starting point. Factors that can affect the profile include the
type of soldering system in use, density and types of
components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
150°C
150°C
100°C
100°C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
140°C
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 177 –189°C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
STEP 5
STEP 6 STEP 7
STEP 4
HEATING
VENT COOLING
HEATING
ZONES 4 & 7
ZONES 3 & 6
205° TO
“SPIKE”
“SOAK”
219°C
170°C
PEAK AT
SOLDER
160°C
JOINT
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 4. Typical Solder Heating Profile
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
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