SY10E160JC datasheet, PDF - EEWORLD Datasheet

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SY10E160JC: DescriptionParity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, PLASTIC, LCC-28; Categorylogic logic; File Size59KB，5 Pages; ManufacturerMicrel ( Microchip ); Websitehttps://www.microchip.com

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SY10E160JC Overview

Parity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, PLASTIC, LCC-28

SY10E160JC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micrel ( Microchip )
package instruction	PLASTIC, LCC-28
Reach Compliance Code	not_compliant
series	10E
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.48 mm
Logic integrated circuit type	PARITY GENERATOR/CHECKER
Humidity sensitivity level	1
Number of digits	12
Number of functions	1
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature
Output characteristics	OPEN-EMITTER
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	240
power supply	-5.2 V
propagation delay (tpd)	0.95 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	11.48 mm

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Micrel, Inc.

12-BIT PARITY

GENERATOR/CHECKER

SY10E160

SY100E160

SY10E160

SY100E160

FEATURES

Provides odd-HIGH parity of 12 inputs

Extended 100E V

range of –4.2V to –5.5V

Output register with Shift/Hold capability

900ps max. D to Q, /Q output

Enable control

Asynchronous Register Reset

DESCRIPTION

The SY10/100E160 are high-speed, 12-bit parity

generator/checkers with differential outputs, for use in

new, high-performance ECL systems. The output Q takes

on a logic HIGH value only when an odd number of inputs

are at a logic HIGH. A logic HIGH on the enable input (EN)

forces the output Q to a logic LOW.

An additional feature of the E160 is the output register.

Two multiplexers and their associated signals control the

data, loading the new parity data or shifting external data

in. To hold the present data, the Hold signal (HOLD) must

be at a logic LOW level. If the HOLD signal is at a logic

HIGH, the data present at the Q output is passed through

the first multiplexer. Taking the Shift signal (SHIFT) to a

logic HIGH will shift the data at the S-IN pin into the output

of the first multiplexer is then passed through to the register.

The register itself is clocked on the rising edge of CLK

or CLK

(or both). The presence of a logic HIGH on the

reset pin (R) forces the register output Y to a logic LOW.

Differential outputs

Fully compatible with industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

Fully compatible with Motorola MC10E/100E160

Available in 28-pin PLCC package

BLOCK DIAGRAM

HOLD

S-IN

SHIFT

CLK

MUX

SEL

MUX

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: F

Amendment: /0

Issue Date: March 2006

SY10E160JC Related Products

	SY10E160JC	SY100E160JZ	SY100E160JC	SY10E160JZ
Description	Parity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, PLASTIC, LCC-28	Parity Generator/Checker, 100E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28	Parity Generator/Checker, 100E Series, 12-Bit, Complementary Output, ECL, PQCC28, PLASTIC, LCC-28	Parity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28
Maker	Micrel ( Microchip )	Micrel ( Microchip )	Micrel ( Microchip )	Micrel ( Microchip )
package instruction	PLASTIC, LCC-28	QCCJ,	PLASTIC, LCC-28	QCCJ,
Reach Compliance Code	not_compliant	unknown	not_compliant	compli
series	10E	100E	100E	10E
JESD-30 code	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e0	e3	e0	e3
length	11.48 mm	11.48 mm	11.48 mm	11.48 mm
Logic integrated circuit type	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER
Number of digits	12	12	12	12
Number of functions	1	1	1	1
Number of terminals	28	28	28	28
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	QCCJ	QCCJ
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
propagation delay (tpd)	0.95 ns	0.95 ns	0.95 ns	0.95 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	4.57 mm	4.57 mm	4.57 mm
surface mount	YES	YES	YES	YES
technology	ECL	ECL	ECL	ECL
Temperature level	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn85Pb15)	MATTE TIN	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)
Terminal form	J BEND	J BEND	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
width	11.48 mm	11.48 mm	11.48 mm	11.48 mm
Is it Rohs certified?	incompatible	-	incompatible	conform to
Humidity sensitivity level	1	-	1	2
Peak Reflow Temperature (Celsius)	240	-	240	260
Maximum time at peak reflow temperature	30	-	30	NOT SPECIFIED

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