HD74ACT163RP datasheet, PDF - EEWORLD Datasheet

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HD74ACT163RP: DescriptionBinary Counter, Synchronous, Up Direction, CMOS, PDSO16, FP-16DN; Categorylogic logic; File Size69KB，12 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD74ACT163RP Overview

Binary Counter, Synchronous, Up Direction, CMOS, PDSO16, FP-16DN

HD74ACT163RP Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Hitachi （Renesas ）
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	unknown
Counting direction	UP
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	9.9 mm
Load capacitance (CL)	50 pF
Load/preset input	YES
Logic integrated circuit type	BINARY COUNTER
Maximum Frequency@Nom-Sup	105000000 Hz
Operating mode	SYNCHRONOUS
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.9 mm

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HD74ACT161/HD74ACT163

Synchronous Presettable Binary Counter

ADE-205-402 (Z)

1st. Edition

Sep. 2000

Description

The HD74ACT161 and HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are

synchronously presettable for application in programmable dividers and have two types of Count Enable

inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The

HD74ACT161 have an asynchronous Master Reset input that overrides all other inputs and forces the

outputs Low. The HD74ACT163 has a Synchronous Reset input that overrides counting and parallel

loading and allows the outputs to be simultaneously reset on the rising edge of the clock.

Features

•

Synchronous Counting and Loading

•

High-Speed Synchronous Expansion

•

Typical Count Rate of 125 MHz

•

Outputs Source/Sink 24 mA

•

HD74ACT161 and HD74ACT163 have TTL-Compatible Inputs

HD74ACT161/HD74ACT163

Pin Names

CEP

CET

(HD74ACT161)

(HD74ACT163)

to P

to Q

Count Enable Parallel Input

Count Enable Trickle Input

Clock Pulse Input

Asynchronous Master Reset Input

Synchronous Reset Input

Parallel Data Inputs

Parallel Enable Input

Flip-Flop Outputs

Terminal Count Output

Functional Description

The HD74ACT161 and HD74ACT163 count in modulo-16 binary sequence. From state 15 (HHHH) they

increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer.

Thus all changes of the Q outputs (except due to Master Reset of the HD74ACT161) occur as a reset of,

and synchronous with, the Low-to-High transition of the CP input signal. The circuits have four

fundamental modes of operation, in order of precedence: asynchronous reset (HD74ACT161),

synchronous reset (HD74ACT163), parallel load, countup and hold. Five control inputs – Master Reste

(MR, HD74ACT161), Synchronous Reset (SR, HD74ACT163), Parallel Enable (PE), Count Enable

Parallel (CEP) and Count Enable Trickle (CET) – determine the mode of operation, as shown in the Mode

Select Table. A Low signal on

overrides all other inputs and asynchronously forces all outputs Low.

A Low signal on

overrides counting and parallel loading and allows all outputs to go Low on the next

rising edge of CP. A Low signal on

overrides counting and allows information on the Parallel Data

(Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With

and

(HD74ACT161)

(HD74ACT163) High, CEP and CET permit counting when both are High. Conversely, a Low

signal on either CEP or CET inhibits counting.

The HD74ACT161 and HD74ACT163 use D-type edge-triggered flip-flops and changing the

SR, PE,

CEP

and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup

and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is

High when CET is High and counter is in state 15. To implement synchronous multistage counters, the TC

outputs can be used with the CEP and CET inputs in two different ways. The TC output is subject to

decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or

asynchronous reset for flip-flops, counters or registers.

Logic Equations: Count Enable = CEP•CET•PE

TC = Q

•Q

•CET

HD74ACT163RP Related Products

	HD74ACT163RP	HD74ACT163FP	HD74ACT163P	HD74ACT163T
Description	Binary Counter, Synchronous, Up Direction, CMOS, PDSO16, FP-16DN	Binary Counter, Synchronous, Up Direction, CMOS, PDSO16, FP-16DA	Binary Counter, Synchronous, Up Direction, CMOS, PDIP16, DP-16	Binary Counter, Synchronous, Up Direction, CMOS, PDSO16, TTP-16DA
Is it Rohs certified?	incompatible	conform to	incompatible	incompatible
Maker	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）
Parts packaging code	SOIC	SOIC	DIP	SOIC
package instruction	SOP, SOP16,.25	SOP, SOP16,.3	DIP, DIP16,.3	TSSOP, TSSOP16,.25
Contacts	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown
Counting direction	UP	UP	UP	UP
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16	R-PDSO-G16
length	9.9 mm	10.06 mm	19.2 mm	5 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Load/preset input	YES	YES	YES	YES
Logic integrated circuit type	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
Maximum Frequency@Nom-Sup	105000000 Hz	105000000 Hz	105000000 Hz	105000000 Hz
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Number of functions	1	1	1	1
Number of terminals	16	16	16	16
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	DIP	TSSOP
Encapsulate equivalent code	SOP16,.25	SOP16,.3	DIP16,.3	TSSOP16,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	IN-LINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	2.2 mm	5.06 mm	1.1 mm
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	YES	NO	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	THROUGH-HOLE	GULL WING
Terminal pitch	1.27 mm	1.27 mm	2.54 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	3.9 mm	5.5 mm	7.62 mm	4.4 mm
JESD-609 code	e0	-	e0	e0
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)

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