HD74ACT161/HD74ACT163
Synchronous Presettable Binary Counter
REJ03D0279–0200Z
(Previous ADE-205-402 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74ACT161 and HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are
synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a
Terminal Count output for versatility in forming synchronous multistage counters. The HD74ACT161 have an
asynchronous Master Reset input that overrides all other inputs and forces the outputs Low. The HD74ACT163 has a
Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset
on the rising edge of the clock.
Features
•
Synchronous Counting and Loading
•
High-Speed Synchronous Expansion
•
Typical Count Rate of 125 MHz
•
Outputs Source/Sink 24 mA
•
HD74ACT161 and HD74ACT163 have TTL-Compatible Inputs
•
Ordering Information: Ex. HD74ACT161
Part Name
Package Type
Package Code Package Abbreviation Taping Abbreviation (Quantity)
FP-16DAV
FP
RP
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
HD74ACT161FPEL SOP-16 pin (JEITA)
HD74ACT161RPEL SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
*R
1
CP 2
P
0
3
P
1
4
P
2
5
P
3
6
CEP 7
GND 8
(Top view)
16 V
CC
15 TC
14 Q
0
13 Q
1
12 Q
2
11 Q
3
10 CET
9
PE
Rev.2.00, Jul.16.2004, page 1 of 8
HD74ACT161/HD74ACT163
Logic Symbol
PE P
0
P
1
P
2
P
3
CEP
CET
CP
*R Q
0
Q
1
Q
2
Q
3
*
MR
for HD74ACT161
SR
for HD74ACT163
TC
Pin Names
CEP
CET
CP
MR
(HD74ACT161)
SR
(HD74ACT163)
P
0
to P
3
PE
Q
0
to Q
3
TC
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Asynchronous Master Reset Input
Synchronous Reset Input
Parallel Data Inputs
Parallel Enable Input
Flip-Flop Outputs
Terminal Count Output
Functional Description
The HD74ACT161 and HD74ACT163 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the
Q outputs (except due to Master Reset of the HD74ACT161) occur as a reset of, and synchronous with, the Low-to-
High transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence:
asynchronous reset (HD74ACT161),
synchronous reset (HD74ACT163), parallel load, countup and hold. Five control inputs – Master Reste (MR,
HD74ACT161), Synchronous Reset (SR, HD74ACT163), Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET) – determine the mode of operation, as shown in the Mode Select Table. A Low signal on
MR
overrides all other inputs and asynchronously forces all outputs Low. A Low signal on
SR
overrides counting and
parallel loading and allows all outputs to go Low on the next rising edge of CP. A Low signal on
PE
overrides counting
and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP.
With
PE
and
MR
(HD74ACT161) or
SR
(HD74ACT163) High, CEP and CET permit counting when both are High.
Conversely, a Low signal on either CEP or CET inhibits counting.
The HD74ACT161 and HD74ACT163 use D-type edge-triggered flip-flops and changing the
SR, PE,
CEP and CET
inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed. The Terminal Count (TC) output is High when CET is High and counter
is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET
inputs in two different ways. The TC output is subject to decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers.
Logic Equations: Count Enable = CEP•CET•PE
TC = Q
0
•Q
1
•Q
2
•Q
3
•CET
Rev.2.00, Jul.16.2004, page 2 of 8
HD74ACT161/HD74ACT163
Mode Select Table
SR*
SR
1
L
H
H
H
H
Note:
X
L
H
H
H
PE
X
X
H
L
X
CET
X
X
H
X
L
CEP
Action on the Rising Clock Edge (
Reset (Clear)
Load (Pn
→
Qn)
Count (Increment)
No change (Hold)
No change (Hold)
)
1. For HD74ACT163
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
State Diagram
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
Block Diagram
P
0
PE
’161 ’163
CEP
CET
’163
ONRY
P
1
P
2
P
3
TC
CP
CP
’161
ONRY
CP
D CP D
C
D
Q Q
Q
0
Q
0
DETAIL A
DETAIL A
DETAIL A
DETAIL A
MR
’161
SR
’163
Q
0
Q
1
Q
2
Q
3
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 3 of 8
HD74ACT161/HD74ACT163
Absolute Maximum Ratings
Item
Supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or ground current per output pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
Tstg
Ratings
–0.5 to 7
–20
20
–0.5 to Vcc+0.5
–50
50
–0.5 to Vcc+0.5
±50
±50
–65 to +150
Unit
V
mA
mA
V
mA
mA
V
mA
mA
°C
Condition
V
I
= –0.5V
V
I
= Vcc+0.5V
V
O
= –0.5V
V
O
= Vcc+0.5V
Recommended Operating Conditions
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
0.8 to 2.0 V
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
Ratings
2 to 6
0 to V
CC
–40 to +85
8
V
V
°C
ns/V
V
CC
= 4.5V
V
CC
= 5.5V
Unit
Condition
DC Characteristics
Item
Sym-
bol
V
IH
V
IL
Output voltage
V
OH
V
CC
(V)
min.
Input voltage
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
4.5
5.5
4.5
5.5
Input current
I
CC
/input current
Dynamic output
current*
Quiescent supply
current
I
IN
I
CCT
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
2.0
2.0
—
—
4.4
5.4
3.94
4.94
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
1.5
1.5
1.5
4.49
5.49
—
—
0.001
0.001
—
—
—
0.6
—
—
—
max.
—
—
0.8
0.8
—
—
—
—
0.1
0.1
0.32
0.32
±0.1
—
—
—
8.0
Ta = –40 to
+85°C
°
min.
max.
2.0
2.0
—
—
4.4
5.4
3.80
4.80
—
—
—
—
—
—
86
–75
—
—
—
0.8
0.8
—
—
—
—
0.1
0.1
0.37
0.37
±1.0
1.5
—
—
80
µA
mA
mA
mA
µA
V
Unit
Condition
V
V
OUT
= 0.1 V or Vcc–0.1 V
V
OUT
= 0.1 V or Vcc–0.1 V
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
V
IN
= V
CC
or GND
V
IN
= V
CC
–2.1 V
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
I
OL
= 24 mA
I
OL
= 24 mA
I
OH
= –24 mA
I
OH
= –24 mA
*Maximum
test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 4 of 8
HD74ACT161/HD74ACT163
AC Characteristics: HD74ACT161
Ta = +25°C
C
L
= 50 pF
Item
Maximum count
frequency
Propagation delay
CP to Q
n
(PE Input
HIGH or LOW)
Propagation delay
CP to Q
n
(PE Input
HIGH or LOW)
Propagation delay
CP to TC
Propagation delay
CP to TC
Propagation delay
CET to TC
Propagation delay
CET to TC
Propagation delay
MR
to Q
n
Propagation delay
MR
to TC
Note:
Symbol
f
max
t
PLH
V
CC
(V)*
1
Min
5.0
115
5.0
1.0
Typ
125
5.5
Max
—
9.5
Ta = –40°C to +85°C
C
L
= 50 pF
Min
100
1.0
—
10.5
Max
MHz
ns
Unit
t
PLH
5.0
1.0
6.0
10.5
1.0
11.5
ns
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
5.0
5.0
5.0
5.0
5.0
5.0
1.0
1.0
1.0
1.0
1.0
1.0
7.0
8.0
5.5
6.0
6.0
8.0
11.0
12.5
8.5
9.5
10.0
13.5
1.0
1.0
1.0
1.0
1.0
1.0
12.5
13.5
10.0
10.5
11.0
14.5
ns
ns
ns
ns
ns
ns
1. Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74ACT161
Ta = +25°C
C
L
= 50 pF
Item
Set-up time, HIGH or LOW
P
n
to CP
Hold time, HIGH or LOW
P
n
to CP
Setup time, HIGH or LOW
MR
to CP
Hold time, HIGH or LOW
MR
to CP
Setup time, HIGH or LOW
PE
to CP
Hold time, HIGH or LOW
PE
to CP
Setup time, HIGH or LOW
CEP or CET to CP
Hold time, HIGH or LOW
CEP or CET to CP
Clock pulse width (Load)
HIGH or LOW
Clock pulse width (Count)
HIGH or LOW
MR
pulse width, LOW
Recovery time
MR
to CP
Note:
Symbol V
CC
(V)*
1
Typ
5.0
4.0
t
su
t
h
t
su
t
h
t
su
t
h
t
su
t
h
t
w
t
w
t
w
t
rec
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
–5.0
4.0
–5.5
4.0
–5.5
2.5
–3.0
2.0
2.0
3.0
0
Ta = –40°C
to +85°C
C
L
= 50 pF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Guaranteed Minimum
9.5
11.5
0
8.5
–0.5
8.5
–0.5
5.5
0
3.0
3.0
3.0
0
0
9.5
–0.5
9.5
–0.5
6.5
0
3.5
3.5
7.5
0.5
1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 8
京公网安备 11010802033920号
EEWORLD
