CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device, at these or any other conditions above those listed in the operational sections of this specification, is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Note:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379 for details.
Electrical Specifications
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND.
SYMBOL
IccdSby
IccdRd
IccdWr
I
LkgDig
I
LkgDCP
VDDRamp
t
DCP
(Note 13)
t
D
PARAMETER
Standby Current at VDD
Read Current at VDD
Write Current at VDD
Leakage Current at Pins SDA, SCL,
and WP
Leakage Current at RH, RW, RL
VDD Power-Up Ramp Rate
DCP Wiper Response Time
Power-Up Delay
SCL falling edge of last bit of DCP Data Byte to
wiper change
VDD above 2.6V, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby
state
10
W and U versions, respectively. T
A
= 25°C.
Measured between R
H
and R
L
pins.
T
A
= 25°C. Measured between R
H
and R
L
pins.
V
DD
= 3.3V @ 25°C. Wiper current = V
DD
/R
Total
7
-20
100
10, 50
20
300
TEST CONDITIONS
Serial interface in standby
Reading with 400kHz at SCL
Writing to EEPROM
Pin voltage from GND to VDD
Pin voltage from GND to VDD
-10
-1
0.2
1.5
3
MIN
TYP
(Note 1)
MAX
10
1
5
10
1
UNIT
µA
mA
mA
µA
µA
V/ms
µs
ms
CH/CW/CL
(Note 13)
R
Total
RH, RW, RL Pin Capacitance
Total Resistance
R
Total
Tolerance
pF
kΩ
%
Ω
Bits
R
Wiper
Wiper Resistance
DCP Resolution
DCP IN VOLTAGE DIVIDER MODE
(0V at RL, VCC at RH; measured at RW unloaded)
FSerror
(Note 2, 3)
ZSerror
(Note 2, 4)
TC
V
(Note 7, 13)
Full-Scale Error
U option
W option
Zero-Scale Error
U option
W option
Ratiometric Temperature
Coefficient
DCP Register between 10 hex and 6F hex
Monotonic over all tap positions
-0.75
-1
-2
-5
0
0
-1
-1
1
1
±4
0.75
1
0
0
2
5
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
DNL (Note 2, 5) Differential Non-Linearity
INL (Note 2, 6) Integral Non-Linearity
3
FN8243.1
April 17, 2006
ISL96017
Electrical Specifications
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
DCP IN RESISTOR MODE
(Measurements between RH and RW with RL not connected)
R
127
(Note 8) Resistance Offset.
U version - DCP Register set to 7F hex.
Measured between R
H
and R
W
pins.
W version - DCP Register set to 7F hex.
Measured between R
H
and R
W
pins.
TC
R
(Note 11,13)
RDNL
(Note 8,9)
RINL
(Note 8,10)
Resistance Temperature Coefficient
Resistance Differential Non-
Linearity
Resistance Integral Non-Linearity
-0.75
-1
0
0.5
1
±100
0.75
1
2
5
MI
MI
ppm/°C
MI
(Note 1)
MI
(Note 1)
EEPROM SPECS
EEPROM Endurance
EEPROM Retention
t
WC
(Note 12) Non-Volatile Write Cycle Time
SERIAL INTERFACE SPECS
V
IL
V
IH
Hysteresis
V
OL
Cpin
f
SCL
t
IN
t
AA
t
BUF
WP, SDA, and SCL Input Buffer
LOW Voltage
WP, SDA and SCL Input Buffer
HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 4mA
WP, SDA, and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs.
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VDD during
the following START condition
Measured at the 30% of VDD crossing
Measured at the 70% of VDD crossing
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
From SDA falling edge crossing 30% of VDD to
SCL falling edge crossing 70% of VDD
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
From SCL rising edge crossing 70% of VDD to
SDA entering the 30% to 70% of VDD window
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VDD
1300
-0.3
0.7*
VDD
0.05*
VDD
0
0.4
10
400
50
900
0.3*
VDD
VDD
+0.3
V
V
V
V
pF
kHz
ns
ns
ns
At 55°C
1,000,000
50
6
12
Cycles
Years
ms
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
1300
600
600
600
100
ns
ns
ns
ns
ns
t
HD:DAT
t
SU:STO
Input Data Hold Time
STOP Condition Setup Time
0
600
ns
ns
4
FN8243.1
April 17, 2006
ISL96017
Electrical Specifications
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND.
(Continued)
SYMBOL
t
HD:STO
t
DH
PARAMETER
STOP Condition Hold Time
Output Data Hold Time
TEST CONDITIONS
From SDA rising edge to SCL falling edge. Both
crossing 70% of VDD
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window
From 30% to 70% of VDD
From 70% to 30% of VDD
Total on-chip and off-chip
MIN
600
0
TYP
(Note 1)
MAX
UNIT
ns
ns
t
R
t
F
Cb
Rpu
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
20+
0.1*Cb
20+
0.1*Cb
10
1
250
250
400
ns
ns
pF
kΩ
SDA and SCL Bus Pull-Up Resistor Maximum is determined by t
R
and t
F
Off-Chip
For Cb = 400pF, max is about 2~2.5kΩ
For Cb = 40pF, max is about 15~20kΩ
WP Setup Time
WP Hold Time
Before START condition
After STOP condition
t
SU:WP
t
HD:WP
NOTES:
600
600
ns
ns
2. Typical values are for T
A
= 25°C and V
DD
= 3.3V.
3. LSB = (V(RW)
127
– V(RW)
0
)/127. V(RW)
127
and V(RW)
0
are the voltage at pin RW for the DCP Register set to 7F hex and 00 hex respectively.
4. FSerror = (V(RW)
127
– VDD)/LSB
5. ZSerror = V(RW)
0
/LSB
6. DNL = [(V(RW)
i
– V(RW)
i-1
)/LSB] – 1, for i from 1 to 127. i is the DCP Register setting.
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