DATASHEET
ISL2110, ISL2111
100V, 3A/4A Peak, High Frequency Half-Bridge Drivers
The
ISL2110, ISL2111
are 100V, high frequency, half-bridge
N-Channel power MOSFET driver ICs. They are based on the
popular HIP2100, HIP2101 half-bridge drivers, but offer
several performance improvements. Peak output
pull-up/pull-down current has been increased to 3A/4A, which
significantly reduces switching power losses and eliminates
the need for external totem-pole buffers in many applications.
Also, the low end of the V
DD
operational supply range has
been extended to 8VDC. The ISL2110 has additional input
hysteresis for superior operation in noisy environments and the
inputs of the ISL2111, like those of the ISL2110, can now
safely swing to the V
DD
supply rail.
FN6295
Rev.7.00
Mar 16, 2017
Features
• Drives N-Channel MOSFET half-bridge
• SOIC, DFN, and TDFN package options
• SOIC, DFN, and TDFN packages compliant with 100V
conductor spacing guidelines per IPC-2221
• Pb-free (RoHS compliant)
• Bootstrap supply max voltage to 114VDC
• On-chip 1W bootstrap diode
• Fast propagation times for multi-MHz circuits
• Drives 1nF load with typical rise/fall times of 9ns/7.5ns
• CMOS compatible input thresholds (ISL2110)
• 3.3V/TTL compatible input thresholds (ISL2111)
• Independent inputs provide flexibility
• No start-up problems
• Outputs unaffected by supply glitches, HS ringing below
ground or HS slewing at high dv/dt
• Low power consumption
• Wide supply voltage range (8V to 14V)
• Supply undervoltage protection
• 1.6W/1W typical output pull-up/pull-down resistance
Related Literature
• For a full list of related documents, visit our website
-
ISL2110, ISL2111
product pages
Applications
• Telecom half-bridge DC/DC converters
• Telecom full-bridge DC/DC converters
• Two-switch forward converters
• Active-clamp forward converters
• Class-D audio amplifiers
+12V
+100V
V
DD
HB
SECONDARY
CIRCUIT
HI
CONTROL
PWM
CONTROLLER
LI
DRIVE
HI
HO
HS
DRIVE
LO
LO
ISL2110
ISL2111
V
SS
REFERENCE
AND
ISOLATION
FIGURE 1. APPLICATION BLOCK DIAGRAM
FN6295 Rev.7.00
Mar 16, 2017
Page 1 of 15
ISL2110, ISL2111
Functional Block Diagram
HB
V
DD
UNDER
VOLTAGE
LEVEL SHIFT
DRIVER
HS
HI
ISL2111
HO
ISL2111
LI
V
SS
UNDER
VOLTAGE
DRIVER
LO
EPAD (DFN Package Only)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best
thermal performance, connect the EPAD to the PCB power ground plane.
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
FN6295 Rev.7.00
Mar 16, 2017
Page 2 of 15
ISL2110, ISL2111
Application Diagrams
+48V
+12V
PWM
ISL2110
ISL2111
SECONDARY
CIRCUIT
ISOLATION
FIGURE 3. TWO-SWITCH FORWARD CONVERTER
+48V
+12V
SECONDARY
CIRCUIT
PWM
ISL2110
ISL2111
ISOLATION
FIGURE 4. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
Ordering Information
PART NUMBER
(Notes
3, 4)
ISL2110ABZ (Note
1)
ISL2110AR4Z (Note
2)
ISL2111ABZ (Note
1)
ISL2111AR4Z (Note
2)
ISL2111ARTZ (Note
2)
ISL2111BR4Z (Note
2)
NOTES:
1. Add “-T” for 2.5k unit tape and reel options. Refer to
TB347
for details on reel specifications.
2. Add “-T” suffix for 6k unit tape and reel options. Refer to
TB347
for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for
ISL2110, ISL2111.
For more information on MSL, see Tech Brief
TB363.
PART
MARKING
2110 ABZ
211 0AR4Z
2111 ABZ
211 1AR4Z
211 1ARTZ
211 1BR4Z
TEMP
RANGE
(°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
PACKAGE
(RoHS COMPLIANT)
8 Ld SOIC
12 Ld 4x4 DFN
8 Ld SOIC
12 Ld 4x4 DFN
10 Ld 4x4 TDFN
8 Ld 4x4 DFN
M8.15
L12.4x4A
M8.15
L12.4x4A
L10.4x4
L8.4x4
PKG.
DWG. #
FN6295 Rev.7.00
Mar 16, 2017
Page 3 of 15
ISL2110, ISL2111
Pin Configurations
ISL2111ARTZ
(10 LD 4x4 TDFN)
ISL2110AR4Z, ISL2111AR4Z
(12 LD 4x4 DFN)
TOP VIEW
VDD
HB
HO
HS
NC
10 LO
9 VSS
8 LI
7 HI
6 NC
TOP VIEW
1
2
3
4
5
VDD
NC
NC
HB
HO
HS
1
2
3
4
5
6
EPAD*
12 LO
11 VSS
10 NC
9
8
7
*EPAD = EXPOSED PAD
NC
LI
HI
ISL2110ABZ, ISL2111ABZ
(8 LD SOIC)
ISL2111BR4Z
(8 LD 4x4 DFN)
TOP VIEW
VDD
HB
HO
HS
1
2
3
4
8
7
6
5
LO
VSS
LI
HI
VDD
HB
HO
HS
TOP VIEW
LO
VSS
LI
HI
1
2
3
4
EPAD*
8
7
6
5
*EPAD = EXPOSED PAD
Pin Descriptions
SYMBOL
VDD
HB
HO
HS
HI
LI
VSS
LO
NC
EPAD
Positive supply to lower gate driver. Bypass this pin to VSS.
High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap
diode is on-chip.
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
High-side input
Low-side input
Chip negative supply, which will generally be ground.
Low-side output. Connect to gate of low-side power MOSFET.
No connect
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
DESCRIPTION
FN6295 Rev.7.00
Mar 16, 2017
Page 4 of 15
ISL2110, ISL2111
Absolute Maximum Ratings
Supply Voltage, V
DD,
V
HB -
V
HS
(Notes
5, 6)
. . . . . . . . . . . . . . . 0.3V to 18V
LI and HI Voltages (Note
6)
. . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+ 0.3V
Voltage on LO (Note
6)
. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+ 0.3V
Voltage on HO (Note
6)
. . . . . . . . . . . . . . . . . . . . . .V
HS
- 0.3V to V
HB
+ 0.3V
Voltage on HS (Continuous) (Note
6)
. . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note
6).
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in V
DD
to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
8 Ld SOIC (Notes
7, 10)
. . . . . . . . . . . . . . . .
95
46
10 Ld TDFN (Notes
8, 9)
. . . . . . . . . . . . . . .
40
2.5
12 Ld DFN (Notes
8, 9)
. . . . . . . . . . . . . . . .
39
2.5
8 Ld DFN (Notes
8, 9).
. . . . . . . . . . . . . . . . .
40
4.0
Max Power Dissipation at +25°C in Free Air
8 Ld SOIC (Notes
7, 10)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
10 Ld TDFN (Notes
8, 9)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
12 Ld DFN (Notes
8, 9)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
8 Ld DFN (Notes
8, 9)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Maximum Recommended Operating
Conditions
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . . .V
HS
+ 7V to V
HS
+ 14V and V
DD
- 1V to V
DD
+ 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. The ISL2110 and ISL2111 are capable of derated operation at supply voltages exceeding 14V.
Figure 24
shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to V
SS
unless otherwise specified.
7.
JA
is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
8.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
9. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
10. For
JC
, the “case temp” location is taken at the package top center.
Electrical Specifications
V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, no load on LO or HO, unless otherwise specified.
T
J
= +25°C
T
J
= -40°C to +125°C
MAX
(Note
11)
UNIT
PARAMETERS
SUPPLY CURRENTS
V
DD
Quiescent Current
V
DD
Quiescent Current
V
DD
Operating Current
V
DD
Operating Current
Total HB Quiescent Current
Total HB Operating Current
HB to V
SS
Current, Quiescent
HB to V
SS
Current, Operating
INPUT PINS
Low Level Input Voltage Threshold
Low Level Input Voltage Threshold
High Level Input Voltage Threshold
High Level Input Voltage Threshold
Input Voltage Hysteresis
Input Pull-Down Resistance
SYMBOL
TEST CONDITIONS
MIN
(Note
11)
TYP
MAX
MIN
(Note
11)
(Note
11)
I
DD
I
DD
I
DDO
I
DDO
I
HB
I
HBO
I
HBS
I
HBSO
ISL2110; LI = HI = 0V
ISL2111; LI = HI = 0V
ISL2110; f = 500kHz
ISL2111; f = 500kHz
LI = HI = 0V
f = 500kHz
LI = HI = 0V; V
HB
= V
HS
= 114V
f = 500kHz; V
HB
= V
HS
= 114V
-
-
-
-
-
-
-
-
0.10
0.30
3.4
3.5
0.10
3.4
0.05
1.2
0.25
0.45
5.0
5.0
0.15
5.0
1.50
-
-
-
-
-
-
-
-
-
0.30
0.55
5.5
5.5
0.20
5.5
10
-
mA
mA
mA
mA
mA
mA
µA
mA
V
IL
V
IL
V
IH
V
IH
V
IHYS
R
I
ISL2110
ISL2111
ISL2110
ISL2111
ISL2110
3.7
1.4
-
-
-
-
4.4
1.8
6.6
1.8
2.2
210
-
-
7.4
2.2
-
-
3.5
1.2
-
-
-
100
-
-
7.6
2.4
-
500
V
V
V
V
V
kΩ
FN6295 Rev.7.00
Mar 16, 2017
Page 5 of 15
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