L2042AF-08TT datasheet, PDF - EEWORLD Datasheet

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L2042AF-08TT: DescriptionPLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8; Categorylogic logic; File Size401KB，9 Pages; ManufacturerPulseCore Semiconductor Corporation; Environmental Compliance

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L2042AF-08TT Overview

PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8

L2042AF-08TT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	PulseCore Semiconductor Corporation
package instruction	TSSOP-8
Reach Compliance Code	unknown
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
length	4.4 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	1
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.7 V
Minimum supply voltage (Vsup)	2.25 V
Nominal supply voltage (Vsup)	2.85 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm
minfmax	75 MHz

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January 2004

rev 1.0

2.5V LCD Panel Reduction IC

Features

FCC approved method of EMI attenuation.

Provides up to 15dB of EMI suppression.

Generates a low EMI spread spectrum clock of the

input frequency.

Input frequency range: 30MHz to 75 MHz.

Optimized for 32.5MHz, 54MHz, and 65MHz.

Internal loop filter minimizes external components

and board space.

Selectable spread deviation.

SSON# control pin for spread spectrum enable

and disable options.

Low cycle-to-cycle jitter.

2.5V or 3.3V operating voltage range.

TTL or CMOS compatible outputs.

Ultra-low power CMOS design.

Supports most mobile graphic accelerator and

LCD timing controller specifications.

Available in 8-pin TSSOP.

L2042A

cost savings by reducing the number of circuit board

layers ferrite beads,

regulations.

The L2042A uses the most efficient and optimized

modulation profile approved by the FCC and is

implemented in a proprietary all digital method.

The L2042A modulates the output of a single PLL in

order to “spread” the bandwidth of a synthesized clock,

and more importantly, decreases the peak amplitudes of

its harmonics. This results in significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’.

shielding and other passive

components that are traditionally required to pass EMI

Applications

The L2042A is targeted towards digital flat panel

applications for Notebook PCs, Palm-size PCs, office

automation equipment, and LCD monitors.

Product Description

The L2042A is a versatile spread spectrum frequency

modulator designed specifically for digital falt panel

applications.

The

L2042A

reduces

electromagnetic

interference (EMI) at the clock source, allowing system

wide reduction of EMI of down stream clock and data

dependent signals. The L2042A allows significant system

Block Diagram

SR0 CP1 CP0 SSON#

VDD

Modulation

CLKIN

Frequency

Divider

Feedback

Divider

PLL

Phase

Detector

Loop

Filter

VCO

Output

Divider

MODOUT

VSS

Alliance Semiconductor

2575, Augustine Drive

•

Santa Clara, CA

•

Tel: 408.855.4900

•

Fax: 408.855.4999

•

www.alsc.com

Notice: The information in this document is subject to change without notice.

L2042AF-08TT Related Products

	L2042AF-08TT	L2042AF-08TR
Description	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, TSSOP-8
Is it Rohs certified?	conform to	conform to
Maker	PulseCore Semiconductor Corporation	PulseCore Semiconductor Corporation
package instruction	TSSOP-8	TSSOP-8
Reach Compliance Code	unknown	unknown
Input adjustment	STANDARD	STANDARD
JESD-30 code	R-PDSO-G8	R-PDSO-G8
length	4.4 mm	4.4 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1
Number of terminals	8	8
Actual output times	1	1
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	3.7 V	3.7 V
Minimum supply voltage (Vsup)	2.25 V	2.25 V
Nominal supply voltage (Vsup)	2.85 V	2.85 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	3 mm	3 mm
minfmax	75 MHz	75 MHz

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