GM71C(S)17403C/CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
The GM71C(S)17403C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71C(S)17403C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71C(S)17403C/CL
offers Extended Data Out (EDO) Mode as a
high speed access mode. Multiplexed address
inputs permit the GM71C(S)17403C/CL to be
packaged in a standard 300 mil 24(26) pin SOJ
and a standard 300mil 24(26) pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include
single power supply 5V+/-10% tolerance, direct
interfacing capability with high performance
logic families such as Schottky TTL.
Features
* 4,194,304 Words x 4 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
t
RAC
t
CAC
GM71C(S)17403C/CL-5
GM71C(S)17403C/CL-6
GM71C(S)17403C/CL-7
50
60
70
13
15
18
t
RC
84
104
124
t
HPC
20
25
30
Pin Configuration
24(26) SOJ
V
CC
I/O1
I/O2
WE
RAS
NC
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
26
25
24
23
22
21
* Low Power
Active : 660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
: 0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Battery Backup Operation (L-version)
* Test Function : 16bit parallel test mode
24(26) TSOP II
V
SS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
CC
I/O1
I/O2
WE
RAS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
8
9
10
11
12
13
19
18
17
16
15
14
8
9
10
11
12
13
19
18
17
16
15
14
(Top View)
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
Pin Description
Pin
A0-A10
A0-A10
I/O1-I/O4
RAS
CAS
Function
Address Inputs
Refresh Address Inputs
Data-input/Data-output
Row Address Strobe
Column Address Strobe
Pin
WE
OE
V
CC
V
SS
NC
Function
Read/Write Enable
Output Enable
Power (+5V)
Ground
No Connection
Ordering Information
Type No.
GM71C(S)17403CJ/CLJ-5
GM71C(S)17403CJ/CLJ-6
GM71C(S)17403CJ/CLJ-7
GM71C(S)17403CT/CLT-5
GM71C(S)17403CT/CLT-6
GM71C(S)17403CT/CLT-7
Access Time
50ns
60ns
70ns
50ns
60ns
70ns
Package
300 Mil
24(26) Pin
Plastic SOJ
300 Mil
24(26) Pin
Plastic TSOP II
Absolute Maximum Ratings*
Symbol
T
A
T
STG
V
IN
/V
OUT
V
CC
I
OUT
P
D
Parameter
Ambient Temperature under Bias
Storage Temperature (Plastic)
Voltage on any Pin Relative to V
SS
Voltage on V
CC
Relative to V
SS
Short Circuit Output Current
Power Dissipation
Rating
0 ~ 70
-55 ~ 125
-1.0 ~ 7.0
-1.0 ~ 7.0
50
1.0
Unit
C
C
V
V
mA
W
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions
(T
A
= 0 ~ 70C)
Symbol
V
CC
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Min
4.5
2.4
-1.0
Typ
5.0
-
-
Max
5.5
6.5
0.8
Unit
V
V
V
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
DC Electrical Characteristics
(V
CC
= 5.0V+/-10%, V
SS
= 0V, T
OPR
= 0 ~ 70C)
Symbol
V
OH
V
OL
I
CC1
Parameter
Output Level
Output "H" Level Voltage (I
OUT
= -2mA
)
Output Level
Output "L" Level Voltage (I
OUT
=
2
mA)
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling
:
t
RC
=
t
RC
min)
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = V
IH
,
D
OUT
=
High-Z)
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t
RC
= t
RC
min)
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(t
HPC
= t
HPC
min)
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= V
CC
- 0.2V, D
OUT
= High-Z)
CAS-before-RAS Refresh Current
(t
RC
= t
RC
min)
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
Min
2.0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
V
CC
0.4
120
110
100
2
100
90
80
90
80
70
1
150
100
90
80
350
Unit
V
V
Note
mA
1, 2
I
CC2
mA
I
CC3
mA
2
I
CC4
mA
1, 3
I
CC5
mA
uA
mA
5
I
CC6
I
CC7
Battery Backup Operating Current(Standby with CBR Refresh)
(CBR refresh, t
RC
= 62.5us
,
t
RAS
<=
0.3
us,
D
OUT
=
High-Z, CMOS interface)
Standby Current RAS = V
IH
CAS = V
IL
D
OUT
=
Enable
Input Leakage Current
Any Input (0V
<=
V
IN
<=
6V)
Output Leakage Current
(D
OUT
is Disabled, 0V
<=
V
OUT
<= 6
V)
uA
4,5
I
CC8
-
5
mA
1
I
L(I)
I
L(O)
-10
-10
10
10
uA
uA
Note: 1. I
CC
depends on output load condition when the device is selected.
I
CC
(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = V
IL
.
3. Address can be changed once or less while CAS = V
IH
.
4. CAS = L (<=0.2) while RAS = L (<=0.2).
5. L-version.
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
Capacitance
(V
CC
= 5V+/-10%, T
A
= 25C)
Symbol
C
I1
C
I2
C
I/O
Parameter
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
Min
-
-
-
Max
5
7
7
Unit
pF
pF
pF
Note
1
1
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = V
IH
to disable D
OUT
.
AC Characteristics
(V
CC
= 5V+/-10%, T
A
= 0 ~ 70C, Notes 1, 2, 18, 19)
Test Conditions
Input rise and fall times: 2 ns
Input timing reference levels: 0.8V, 2.4V
Output timing reference levels: 0.8V, 2.0V
Output load : 1 TTL gate + C
L
(100pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Parameter
Random Read or Write Cycle Time
RAS Precharge Time
CAS Precharge Time
RAS Pulse Width
CAS Pulse Width
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
OE to D
IN
Delay Time
OE Delay Time from D
IN
CAS Delay Time from D
IN
Transition Time (Rise and Fall)
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403
C/CL-6
C/CL-7
C/CL-5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Min Max Min Max Min Max
t
RC
t
RP
t
CP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
ODD
t
DZO
t
DZC
t
T
84
30
7
-
-
-
104
40
10
-
-
-
124
50
13
-
-
-
50
10,000
7
10,000
0
7
0
7
11
9
10
35
5
13
0
0
2
-
-
-
-
37
25
-
-
-
-
-
-
50
60
10,000
10
10,000
0
10
0
10
14
12
13
40
5
15
0
0
2
-
-
-
-
45
30
-
-
-
-
-
-
50
70
10,000
13
10,000
0
10
0
13
14
12
13
45
5
18
0
0
2
-
-
-
-
52
35
-
-
-
-
-
-
50
21
22
3
4
24
5
6
6
7
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
Read Cycle
Symbol
Parameter
Access Time from RAS
Access Time from CAS
Access Time from Address
Access Time from OE
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
CAS to Output in Low-Z
Output Data Hold Time
Output Data Hold Time from OE
Output Buffer Turn-off Time
Output Buffer Turn-off Time to OE
CAS to D
IN
Delay Time
Read Command Hold Time from RAS
Output Data hold Time from RAS
Output Buffer turn off to RAS
Output Buffer turn off to WE
WE to D
IN
Delay Time
RAS to D
IN
Delay Time
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
C/CL-7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
8,9,19
9,10,17,19
9,11,17,19
Min Max
Min Max Min Max
-
-
-
-
0
0
5
30
18
0
3
3
-
-
15
60
3
-
-
15
15
60
15
30
15
-
-
-
-
-
-
-
-
15
15
-
-
-
15
15
-
-
-
-
-
-
0
0
5
35
23
0
3
3
-
-
18
70
3
-
-
18
18
70
18
35
18
-
-
-
-
-
-
-
-
15
15
-
-
-
15
15
-
-
t
RAC
t
CAC
t
AA
t
OAC
t
RCS
t
RCH
t
RRH
t
RAL
t
CAL
t
CLZ
t
OH
t
OHO
t
OFF
t
OEZ
t
CDD
t
RCHR
t
OHR
t
OFR
t
WEZ
t
WDD
t
RDD
-
-
-
-
0
0
5
25
15
0
3
3
-
-
13
50
3
-
-
13
13
50
13
25
13
-
-
-
-
-
-
-
-
13
13
-
-
-
13
13
-
-
9
12
12
13
13,23
5
13,23
13
Rev 0.1 / Apr’01
京公网安备 11010802033920号
EEWORLD
