550HFFREQBGR datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 550HFFREQBGR

550HFFREQBGR: DescriptionCMOS Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-6; CategoryPassive components oscillator; File Size691KB，45 Pages; ManufacturerSilicon Laboratories Inc

Download Datasheet Parametric View All

550HFFREQBGR Overview

CMOS Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-6

550HFFREQBGR Parametric

Parameter Name	Attribute value
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	COMPLEMENTARY OUTPUT; TRI-STATE; OUTPUT ENABLE; TAPE AND REEL
Maximum control voltage	2.5 V
Minimum control voltage
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	75 ppm
frequency stability	50%
linearity	10%
Manufacturer's serial number	SI550
Installation features	SURFACE MOUNT
Maximum operating frequency	945 MHz
Minimum operating frequency	10 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES

Preview

Download Datasheet

View All

Si550

O L TA G E

- C

O N T R O L L E D

R Y S TA L

S C I L L A T O R

(V CX O)

10 MH

Z T O

1.4 G H

Features

Available with any-rate output

frequencies from 10 MHz to

945 MHz and selected frequencies

to 1.4 GHz

3rd generation DSPLL

with

superior jitter performance

3x better frequency stability than

SAW based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, & CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Lead-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET / SDH

xDSL

10 GbE LAN / WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

Pin Assignments:

See page 6.

(Top View)

Description

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to

provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike traditional VCXO’s where a different crystal is required for

each output frequency, the Si550 uses one fixed crystal to provide a wide

range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In

addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems. The Si550 IC-based VCXO is

factory configurable for a wide variety of user specifications, including

frequency, supply voltage, output format, tuning slope, and temperature

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

GND

CLK–

CLK+

Functional Block Diagram

CLK–

CLK+

Fixed

Frequency

Any-rate

10-1400 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 0.5 7/06

Si550

Recommended Resources

Diode square rate detection circuit

PTC three-phase asynchronous motor protection circuit three

Make LM1875 sound better

LA4461N circuit

Quadrature Oscillator Using Multiplier 4214

MP3 hardware circuit schematic diagram 08

What are the differences between AC reactors and DC reactors?: [size=5] Common reactors used in power systems include series reactors and shunt reactors. Series reactors are mainly used to limit short-circuit currents. They are also used in filters in series or i...; Jacktang Analogue and Mixed Signal

Problems with sending text messages on a PC: The problem is, after the PC establishes a connection with Nokia, it sends the At+CSCA command and can obtain the SMSC of the SIM card normally. When sending a text message, the string composed of the...; jiyu29009 Embedded System

Arrow SOC Kit Learning Dial Code Lighting: [i=s]This post was last edited by ole007 on 2015-3-2 23:00[/i] [align=center]Learning about Arrow SoCKit: Dial-up Lighting[/align][align=center]Ole007[/align][align=left]When I got the Arrow SoC Kit d...; ole007 FPGA/CPLD

Ask a question about the RO segment in ADS: 1. Is the starting position of the RO segment set in ADS, such as 0x30000000, and the generated .bin file must be placed in this address space to run, or can it run no matter what memory space it is i...; panshiowen Embedded System

Yuan Fang, what do you think of this circuit? (3): [font=宋体]Yuan Fang: Sir, I have been busy these past two days. When I was free, I looked at this circuit, but it was hard to tell how many zeros and poles there were in it... Please tell me clearly......; zjd01 Analogue and Mixed Signal

Does Samsung have an official 2440 wince 6.0 bsp?: Does Samsung have an official 2440 wince 6.0 BSP? Or does anyone have one? Can you please contribute?...; zyandll123 Embedded System

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components