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571BJAFREQDGR

Description
LVDS Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-8
CategoryPassive components    oscillator   
File Size316KB,26 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

571BJAFREQDGR Overview

LVDS Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-8

571BJAFREQDGR Parametric

Parameter NameAttribute value
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTRISTATE; ENABLE/DISABLE FUNCTION; TAPE AND REEL
Maximum control voltage3.3 V
Minimum control voltage
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate130 ppm
frequency stability20%
linearity10%
Manufacturer's serial numberSI571
Installation featuresSURFACE MOUNT
Maximum operating frequency945 MHz
Minimum operating frequency10 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Si 5 7 0 / S i 5 7 1
P
R E L I M I N A R Y
D
A TA
S
H E E T
A
N Y
- R
A T E
I
2
C P
R O G R A M M A B L E
XO/VCXO
Features
Any-rate programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I
2
C serial interface
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
Si5602
Applications
SONET / SDH
xDSL
10 GbE LAN / WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Ordering Information:
See page 21.
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are
user-programmable to any output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz with <1 ppb resolution. The device is programmed
via an I
2
C serial interface. Unlike traditional XO/VCXOs where a different
crystal is required for each output frequency, the Si57x uses one fixed-
frequency crystal and a DSPLL clock synthesis IC to provide any-rate
frequency operation. This IC-based approach allows the crystal resonator to
provide exceptional frequency stability and reliability. In addition, DSPLL
clock synthesis provides superior supply noise rejection, simplifying the task
of generating low-jitter clocks in noisy environments typically found in
communication systems.
Pin Assignments:
See page 20.
(Top View)
SDA
7
NC
1
2
3
8
SCL
6
5
4
V
DD
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK-
CLK+
Si570
SDA
7
Fixed
Frequency
XO
Any-rate
10-1400 MHz
®
DSPLL Clock
Synthesis
V
C
SCL
1
2
3
8
SCL
6
5
4
V
DD
SDA
OE
GND
CLK–
CLK+
Si571 only
ADC
OE
V
C
GND
Si571
Si570/Si571
Rev. 0.31 8/07
Copyright © 2007 by Silicon Laboratories
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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