74AUP2G157GM datasheet, PDF - EEWORLD Datasheet

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74AUP2G157GM: DescriptionMultiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PQCC8; Categorylogic logic; File Size294KB，25 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74AUP2G157GM Overview

Multiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PQCC8

74AUP2G157GM Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	VQCCN,
Reach Compliance Code	compliant
series	AUP/ULP/V
JESD-30 code	S-PQCC-N8
JESD-609 code	e4
length	1.6 mm
Logic integrated circuit type	MULTIPLEXER
Humidity sensitivity level	1
Number of functions	1
Number of entries	2
Output times	1
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	VQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	22.8 ns
Certification status	Not Qualified
Maximum seat height	0.5 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	1.1 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	1.6 mm

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74AUP2G157

Low-power 2-input multiplexer

Rev. 7 — 18 January 2013

Product data sheet

1. General description

The 74AUP2G157 is a single 2-input multiplexer which select data from two data inputs

(I0 and I1) under control of a common data select input (S). The state of the common data

select input determines the particular register from which the data comes. The output

(Y, Y) presents the selected data in the true (non-inverted) and complement form. The

enable input (E) is active LOW. When E is HIGH, the output Y is forced LOW and the

output Y is forced HIGH regardless of all other input conditions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V. This device ensures a very low

static and dynamic power consumption across the entire V

range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits



Wide supply voltage range from 0.8 V to 3.6 V



High noise immunity



Complies with JEDEC standards:



JESD8-12 (0.8 V to 1.3 V)



JESD8-11 (0.9 V to 1.65 V)



JESD8-7 (1.2 V to 1.95 V)



JESD8-5 (1.8 V to 2.7 V)



JESD8-B (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F Class 3A exceeds 5000 V



MM JESD22-A115-A exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Low static power consumption; I

= 0.9

A

(maximum)



Latch-up performance exceeds 100 mA per JESD 78 Class II



Inputs accept voltages up to 3.6 V



Low noise overshoot and undershoot < 10 % of V



OFF

circuitry provides partial Power-down mode operation



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C

74AUP2G157GM Related Products

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Description	Multiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PQCC8	Multiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PDSO8	Multiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PDSO8	Multiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PDSO8	Multiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PDSO8	Multiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PDSO8	Multiplexer, AUP/ULP/V Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, CMOS, PDSO8
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia
package instruction	VQCCN,	VSSOP,	VSON,	VSON,	SON,	VSON,	VSON,
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
series	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V
JESD-30 code	S-PQCC-N8	R-PDSO-G8	R-PDSO-N8	R-PDSO-N8	R-PDSO-N8	R-PDSO-N8	R-PDSO-N8
JESD-609 code	e4	e4	e4	e3	e3	e3	e3
length	1.6 mm	2.3 mm	3 mm	1.35 mm	1.2 mm	1.35 mm	1.95 mm
Logic integrated circuit type	MULTIPLEXER	MULTIPLEXER	MULTIPLEXER	MULTIPLEXER	MULTIPLEXER	MULTIPLEXER	MULTIPLEXER
Humidity sensitivity level	1	1	1	1	1	1	1
Number of functions	1	1	1	1	1	1	1
Number of entries	2	2	2	2	2	2	2
Output times	1	1	1	1	1	1	1
Number of terminals	8	8	8	8	8	8	8
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VQCCN	VSSOP	VSON	VSON	SON	VSON	VSON
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260
propagation delay (tpd)	22.8 ns	22.8 ns	22.8 ns	22.8 ns	22.8 ns	22.8 ns	22.8 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	0.5 mm	1 mm	0.5 mm	0.5 mm	0.35 mm	0.35 mm	0.5 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	0.8 V	0.8 V	0.8 V	0.8 V	0.8 V	0.8 V	0.8 V
Nominal supply voltage (Vsup)	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V	1.1 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)
Terminal form	NO LEAD	GULL WING	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.35 mm	0.3 mm	0.35 mm	0.5 mm
Terminal location	QUAD	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30
width	1.6 mm	2 mm	2 mm	1 mm	1 mm	1 mm	1 mm

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