571BJAFREQDG datasheet, PDF - EEWORLD Datasheet

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571BJAFREQDG: DescriptionLVDS Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-8; CategoryPassive components oscillator; File Size316KB，26 Pages; ManufacturerSilicon Laboratories Inc

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571BJAFREQDG Overview

LVDS Output Clock Oscillator, 10MHz Min, 945MHz Max, ROHS COMPLIANT PACKAGE-8

571BJAFREQDG Parametric

Parameter Name	Attribute value
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRISTATE; ENABLE/DISABLE FUNCTION; TRAY
Maximum control voltage	3.3 V
Minimum control voltage
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	130 ppm
frequency stability	20%
linearity	10%
Manufacturer's serial number	SI571
Installation features	SURFACE MOUNT
Maximum operating frequency	945 MHz
Minimum operating frequency	10 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %

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Si 5 7 0 / S i 5 7 1

R E L I M I N A R Y

A TA

H E E T

N Y

- R

A T E

C P

R O G R A M M A B L E

XO/VCXO

Features

Any-rate programmable output

frequencies from 10 to 945 MHz and

select frequencies to 1.4 GHz

C serial interface

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available LVPECL, CMOS,

LVDS, and CML outputs

Industry-standard 5x7 mm

package

Pb-free/RoHS-compliant

1.8, 2.5, or 3.3 V supply

Si5602

Applications

SONET / SDH

xDSL

10 GbE LAN / WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

Ordering Information:

See page 21.

Description

The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are

user-programmable to any output frequency from 10 to 945 MHz and select

frequencies to 1400 MHz with <1 ppb resolution. The device is programmed

via an I

C serial interface. Unlike traditional XO/VCXOs where a different

crystal is required for each output frequency, the Si57x uses one fixed-

frequency crystal and a DSPLL clock synthesis IC to provide any-rate

frequency operation. This IC-based approach allows the crystal resonator to

provide exceptional frequency stability and reliability. In addition, DSPLL

clock synthesis provides superior supply noise rejection, simplifying the task

of generating low-jitter clocks in noisy environments typically found in

communication systems.

Pin Assignments:

See page 20.

(Top View)

SDA

SCL

GND

CLK–

CLK+

Functional Block Diagram

CLK-

CLK+

Si570

SDA

Fixed

Frequency

Any-rate

10-1400 MHz

DSPLL Clock

Synthesis

SCL

SDA

GND

CLK–

CLK+

Si571 only

ADC

GND

Si571

Si570/Si571

Rev. 0.31 8/07

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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