EEWORLDEEWORLDEEWORLD

Part Number

Search

531AA404M000DG

Description
LVPECL Output Clock Oscillator, 404MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531AA404M000DG Overview

LVPECL Output Clock Oscillator, 404MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531AA404M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency404 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Design of a practical computer multi-point temperature detection system
A practical new computer temperature acquisition system with 89C52 as the core is designed. It uses J-type thermocouple as the temperature measuring element and uses the integrated current temperature...
zzzzer16 Test/Measurement
Aircraft, bold prediction
[i=s]This post was last edited by paulhyde on 2014-9-15 03:37[/i]This year's national competition has aircrafts. Dear, are you and your friends shocked? There are aircrafts, angle sensors, and protrac...
季夏木槿 Electronics Design Contest
[ESP32 Learning] Comparison of file reading speeds of two SDIO methods
SDIO supports 4-wire and 1-wire modes. What is the speed difference between the two modes? We tested it on the ESP32_psRAM_Lobo version. The test program is as follows: 1-line mode: [code]import os im...
dcexpert MicroPython Open Source section
Is it possible to draw a logic diagram based on the following paragraph?
[color=#333333][font=宋体,]Assuming that the neighborhood used by the median filter is 3*3, then 9 data need to be known. [/font][/color] [color=#333333][font=宋体,]Adjacent data in the same row can be ob...
魔人布欧01 FPGA/CPLD
FPGA Training
1. Course Introduction In communication and image processing applications, powerful digital signal processing (DSP) capabilities are required. When the fastest digital signal processor (DSP) still can...
yanchao05 Embedded System
Working principle of electronic tags
The basic working principle of RFID technology is not complicated: after the tag enters the magnetic field, it receives the radio frequency signal sent by the reader, and uses the energy obtained from...
Jacktang RF/Wirelessly

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 665  146  2888  1107  2238  14  3  59  23  46 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号