74AHC273D-Q100 datasheet, PDF - EEWORLD Datasheet

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74AHC273D-Q100: DescriptionD Flip-Flop, AHC/VHC/H/U/V Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20; Categorylogic logic; File Size221KB，19 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74AHC273D-Q100 Overview

D Flip-Flop, AHC/VHC/H/U/V Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20

74AHC273D-Q100 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	SOP-20
Reach Compliance Code	compliant
series	AHC/VHC/H/U/V
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	12.8 mm
Logic integrated circuit type	D FLIP-FLOP
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	21.5 ns
Filter level	AEC-Q100
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	7.5 mm
minfmax	100 MHz

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74AHC273-Q100;

74AHCT273-Q100

Octal D-type flip-flop with reset; positive-edge trigger

Rev. 1 — 27 March 2013

Product data sheet

1. General description

The 74AHC273-Q100; 74AHCT273-Q100 is a high-speed Si-gate CMOS device and is

pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7-A.

The 74AHC273-Q100; 74AHCT273-Q100 has eight edge-triggered, D-type flip-flops with

individual D inputs and Q outputs.

The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops

simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock

transition, is transferred to the corresponding output (Qn) of the flip-flop.

All outputs are forced LOW, independent of clock or data inputs, by a LOW on the MR

input.

The device is useful for applications where only the true output is required and the clock

and master reset are common to all storage elements.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits



Automotive product qualification in accordance with AEC-Q100 (Grade 1)



Specified from

40 C

to +85

C

and from

40 C

to +125

C



Balanced propagation delays



All inputs have Schmitt-trigger actions



Inputs accept voltages higher than V



Ideal buffer for MOS microcontroller or memory



Common clock and master reset



Input levels:



For 74AHC273-Q100: CMOS level



For 74AHCT273-Q100: TTL level



ESD protection:



MIL-STD-883, method 3015 exceeds 2000 V



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0

)



Multiple package options

74AHC273D-Q100 Related Products

	74AHC273D-Q100	74AHCT273BQ-Q100	74AHCT273D-Q100	74AHCT273PW-Q100	74AHC273PW-Q100	74AHC273BQ-Q100
Description	D Flip-Flop, AHC/VHC/H/U/V Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20	D Flip-Flop, AHCT/VHCT/VT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PQCC20	D Flip-Flop, AHCT/VHCT/VT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20	D Flip-Flop, AHCT/VHCT/VT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20	D Flip-Flop, AHC/VHC/H/U/V Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20	D Flip-Flop, AHC/VHC/H/U/V Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PQCC20
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia
package instruction	SOP-20	HVQCCN,	SOP-20	TSSOP-20	TSSOP-20	DHVQFN-20
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
series	AHC/VHC/H/U/V	AHCT/VHCT/VT	AHCT/VHCT/VT	AHCT/VHCT/VT	AHC/VHC/H/U/V	AHC/VHC/H/U/V
JESD-30 code	R-PDSO-G20	R-PQCC-N20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PQCC-N20
JESD-609 code	e4	e4	e4	e4	e4	e4
length	12.8 mm	4.5 mm	12.8 mm	6.5 mm	6.5 mm	4.5 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Humidity sensitivity level	1	1	1	1	1	1
Number of digits	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1
Number of terminals	20	20	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	HVQCCN	SOP	TSSOP	TSSOP	HVQCCN
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260
propagation delay (tpd)	21.5 ns	11.5 ns	11.5 ns	11.5 ns	21.5 ns	21.5 ns
Filter level	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100
Maximum seat height	2.65 mm	1 mm	2.65 mm	1.1 mm	1.1 mm	1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	4.5 V	4.5 V	4.5 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	NO LEAD	GULL WING	GULL WING	GULL WING	NO LEAD
Terminal pitch	1.27 mm	0.5 mm	1.27 mm	0.65 mm	0.65 mm	0.5 mm
Terminal location	DUAL	QUAD	DUAL	DUAL	DUAL	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	7.5 mm	2.5 mm	7.5 mm	4.4 mm	4.4 mm	2.5 mm
minfmax	100 MHz	65 MHz	65 MHz	65 MHz	100 MHz	100 MHz

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