74AHC377-Q100;
74AHCT377-Q100
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 1 — 3 December 2013
Product data sheet
1. General description
The 74AHC377-Q100; 74AHCT377-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A. The 74AHC377-Q100; 74AHCT377-Q100 has eight
edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock
input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to
be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Ideal for addressable register applications
Data enable for address and data synchronization
Eight positive-edge triggered D-type flip-flops
Input levels:
For 74AHC377-Q100: CMOS level
For 74AHCT377-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74AHC377-Q100; 74AHCT377-Q100
Octal D-type flip-flop with data enable; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC377-Q100
74AHC377D-Q100
74AHC377PW-Q100
74AHCT377-Q100
74AHCT377D-Q100
74AHCT377PW-Q100
40 C
to +125
C
40 C
to +125
C
SO20
TSSOP20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT163-1
SOT360-1
40 C
to +125
C
40 C
to +125
C
SO20
TSSOP20
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT163-1
SOT360-1
Description
Version
Type number
4. Functional diagram
Fig 1.
Functional diagram
74AHC_AHCT377_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 December 2013
2 of 17
NXP Semiconductors
74AHC377-Q100; 74AHCT377-Q100
Octal D-type flip-flop with data enable; positive-edge trigger
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Fig 4.
Logic diagram
74AHC_AHCT377_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 December 2013
3 of 17
NXP Semiconductors
74AHC377-Q100; 74AHCT377-Q100
Octal D-type flip-flop with data enable; positive-edge trigger
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
E
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
CP
Q4
D4
D5
Q5
Q6
D6
D7
Q7
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
data enable input (active LOW)
flip-flop output
data input
data input
flip-flop output
flip-flop output
data input
data input
flip-flop output
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
flip-flop output
data input
data input
flip-flop output
flip-flop output
data input
data input
flip-flop output
supply voltage
74AHC_AHCT377_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 December 2013
4 of 17
NXP Semiconductors
74AHC377-Q100; 74AHCT377-Q100
Octal D-type flip-flop with data enable; positive-edge trigger
6. Functional description
Table 3.
Function table
[1]
Control
E
Load 1
Load 0
Hold (do nothing)
l
l
h
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
= LOW-to-HIGH CP transition;
X = don’t care.
Operating mode
Input
CP
X
Dn
h
l
X
X
Output
Qn
H
L
no change
no change
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
20
20
25
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO20 packages: above 70
C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP20 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
74AHC_AHCT377_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 December 2013
5 of 17
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