AS7C33512NTD32A-133TQC datasheet, PDF

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AS7C33512NTD32A-133TQC: DescriptionZBT SRAM, 512KX32, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100; Categorystorage storage; File Size426KB，18 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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AS7C33512NTD32A-133TQC Overview

ZBT SRAM, 512KX32, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C33512NTD32A-133TQC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.8 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	16777216 bit
Memory IC Type	ZBT SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX32
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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April 2005

AS7C33512NTD32A

AS7C33512NTD36A

3.3V 512K × 32/36 Pipelined SRAM with NTD

Features

•

Organization: 524,288 words × 32 or 36 bits

NTD

™

architecture for efficient bus operation

Fast clock speeds to 166 MHz

Fast clock to data access: 3.4/3.8 ns

Fast OE access time: 3.4/3.8 ns

Fully synchronous operation

Asynchronous output enable control

Available in 100-pin TQFP packages

Individual byte write and global write

•

Clock enable for operation hold

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Self-timed write cycles

Interleaved or linear burst modes

Snooze mode for standby operation

Logic block diagram

A[18:0]

Address

Burst logic

CLK

CE0

CE1

CE2

R/W

BWa

BWb

BWc

BWd

ADV / LD

LBO

Write delay

addr. registers

CLK

Control

logic

CLK

Write Buffer

CLK

512K x 32/36

SRAM

Array

DQ[a,b,c,d]

32/36

Data

Input

CLK

32/36

CLK

CEN

CLK

Output

32/36

DQ[a,b,c,d]

Selection guide

-166

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

166

3.4

300

-133

7.5

133

3.8

275

Units

MHz

4/21/05, v 2.8

Alliance Semiconductor

P. 1 of 18

AS7C33512NTD32A/36A

Functional Description

The AS7C33512NTD32A/36A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory

(SRAM) organized as 524,288 words × 32 or 36 bits and incorporates a LATE LATE Write.

This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD

™

) architecture, featuring an enhanced

write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data,

command, and address are all applied to the device on the same clock edge. If a read command follows this write command,

the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce

overall bandwidth for applications requiring random access or read-modify-write operations.

NTD

™

devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or

one-cycle flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read

pipeline to clear. With NTD

™

, write and read operations can be used in any order without producing dead bus cycles.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full

32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is

applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled

for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-

selected by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write

operations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip

select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any

device operations, including burst, can be stalled using the CEN=1, the clock enable input.

The AS7C33512NTD32A/36A operates with a 3.3V ± 5% power supply for the device core (V

). DQ circuits use a separate

power supply (V

DDQ

) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package.

TQFP capacitance

Parameter

Input capacitance

I/O capacitance

* Guaranteed not tested

Symbol

IN*

I/O*

Test conditions

= 0V

OUT

= 0V

Min

Max

Unit

TQFP thermal resistance

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to top of case)

1 This parameter is sampled

Conditions

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

1–layer

4–layer

Symbol

Typical

Units

°C/W

4/21/05, v 2.8

Alliance Semiconductor

P. 4 of 18

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