74AHC74-Q100;
74AHCT74-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 2 — 21 April 2015
Product data sheet
1. General description
The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop
with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It
also has complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the
clock input. Information on the data input is transferred to the Q output on the LOW to
HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to
the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC74-Q100: CMOS level
For 74AHCT74-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74AHC74-Q100; 74AHCT74-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC74-Q100
74AHC74D-Q100
74AHC74PW-Q100
74AHC74BQ-Q100
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO14
TSSOP14
plastic small outline package; 14 leads; body width SOT108-1
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
Description
Version
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
SO14
TSSOP14
plastic small outline package; 14 leads; body width SOT108-1
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74AHCT74-Q100
74AHCT74D-Q100
40 C
to +125
C
74AHCT74PW-Q100
40 C
to +125
C
74AHCT74BQ-Q100
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
4 10
1SD 2SD
2
12
3
11
SD
1Q
1D
Q
D
2D
2Q
1CP
CP
2CP
FF
1Q
Q
2Q
RD
1RD 2RD
1 13
mna418
5
9
6
8
Fig 1.
Functional diagram
74AHC_AHCT74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 21 April 2015
2 of 19
NXP Semiconductors
74AHC74-Q100; 74AHCT74-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
4
1SD
SD
D
CP
FF
Q
RD
1Q
6
4
3
2
1
2D
2CP
SD
D
CP
FF
Q
RD
2Q
8
Q
2Q
9
S
C1
1D
R
6
5
Q
2
3
1D
1CP
1Q
5
1
10
1RD
2SD
12
11
10
11
12
13
S
C1
1D
R
mna419
9
8
13
2RD
mna420
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Q
C
C
C
C
D
C
RD
C
C
Q
C
SD
mna421
CP
C
C
Fig 4.
Logic diagram (one flip-flop)
74AHC_AHCT74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 21 April 2015
3 of 19
NXP Semiconductors
74AHC74-Q100; 74AHCT74-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO14 and TSSOP14
Fig 6.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset direct input (active LOW)
data input
clock input (LOW to HIGH, edge-triggered)
asynchronous set direct input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
complement flip-flop output
true flip-flop output
asynchronous set direct input (active LOW)
clock input (LOW to HIGH, edge-triggered)
data input
asynchronous reset direct input (active LOW)
supply voltage
74AHC_AHCT74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 21 April 2015
4 of 19
NXP Semiconductors
74AHC74-Q100; 74AHCT74-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
6. Functional description
Table 3.
Control
nSD
L
H
L
H
H
[1]
Function table
[1]
Input
nRD
H
L
L
H
H
nCP
X
X
X
nD
X
X
X
L
H
Output
nQ
H
L
H
-
-
nQ
L
H
H
-
-
nQ
n+1
-
-
-
L
H
nQ
n+1
-
-
-
H
L
H = HIGH voltage level;
L = LOW voltage level;
= LOW to HIGH transition;
Q
n+1
= state after the next LOW to HIGH CP transition;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
= l to (V
CC
+ 0.5 V)
[1]
[1]
20
20
25
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
74AHC_AHCT74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 21 April 2015
5 of 19
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