531BA656M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531BA656M000DG

531BA656M000DG: DescriptionLVDS Output Clock Oscillator, 656MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531BA656M000DG Overview

LVDS Output Clock Oscillator, 656MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531BA656M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	656 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Overvoltage and overcurrent protection circuit diagram using NE555

Positive and negative 30V-1A precision CNC DC regulated power supply

Interface circuit for controlling AC loads

Tube ZELL power amplifier circuit diagram

845ddr computer motherboard circuit diagram_33

How to divide nandflash into two fat areas?: I am currently using a Freescale m31+ce5.0 system. After modifying the hive registry, the 512MB nand flash now has a fat partition, and the nand flash disk can be seen after the system starts. I now w...; dfx168 Embedded System

Experts tell us how to make a good FPGA: Da Xia: I have always wanted to make FPGA. I have read a lot of books, but I am still confused. Because most of them are simple examples, and some are a little more complicated. But I always feel that...; heningbo FPGA/CPLD

EVC connection error.: I copied the printer USB program under PB to a folder. Use EVC4 to create a dll project. And include these CH files and set the path. The compilation and connection errors are as follows: Creating lib...; whbahx Embedded System

BMS management chip BQ79606A-Q1 chip temperature sampling consultation: The return value of the DEV_STAT register of BQ79606A-Q1 is abnormal. The GPIO is configured as temperature sensing mode, and the data read from each GPIO is very different. Please guide!!!...; Alic Automotive Electronics

TMS320C6416 timer + interrupt test program: Share a TMS320C6416 timer + interrupt test program DSP model: TMS320C6416 Software development environment: CCS3.3 Test available [size=4][b][/b][/size]...; Jacktang DSP and ARM Processors

Please recommend an ARM9 chip with a relatively high cost performance, thank you: Now I want to use a cost-effective ARM9 chip that can provide two UARTs and a 10/100M Ethernet electrical port. Does anyone have any recommended chips?...; 651076842 ARM Technology

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components