82V2082PF8 datasheet, PDF - EEWORLD Datasheet

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82V2082PF8: DescriptionPCM Transceiver, 1-Func, PQFP80, TQFP-80; CategoryWireless rf/communication Telecom circuit; File Size826KB，88 Pages; ManufacturerIDT (Integrated Device Technology)

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82V2082PF8 Overview

PCM Transceiver, 1-Func, PQFP80, TQFP-80

82V2082PF8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	LQFP, QFP80,.64SQ
Contacts	80
Reach Compliance Code	_compli
ECCN code	EAR99
JESD-30 code	S-PQFP-G80
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	80
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP80,.64SQ
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	0.18 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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DUAL CHANNEL T1/E1/J1 LONG

HAUL/SHORT HAUL LINE INTER-

FACE UNIT

FEATURES:

•

Dual channel T1/E1/J1 long haul/short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024

KHz

Programmable T1/E1/J1 switchability allowing one bill of ma-

terial for any line condition

Single 3.3 V power supply with 5 V tolerance on digital interfaces

Meets or exceeds specifications in

- ANSI T1.102, T1.403 and T1.408

- ITU I.431, G.703, G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR12/13

- AT&T Pub 62411

Software programmable or hardware selectable on:

- Wave-shaping templates for short haul and long haul LBO (Line Build

Out)

- Line terminating impedance (T1:100

Ω,

J1:110

Ω,

E1: 75

Ω/120 Ω)

- Adjustment of arbitrary pulse shape

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

- B8ZS/HDB3/AMI line encoding/decoding

- Active edge of transmit clock (TCLK) and receive clock (RCLK)

- Active level of transmit data (TDATA) and receive data (RDATA)

IDT82V2082

•

- Receiver or transmitter power down

- High impedance setting for line drivers

- PRBS (Pseudo Random Bit Sequence) generation and detection

with 2

-1 PRBS polynomials for E1

- QRSS (Quasi Random Sequence Signals) generation and detection

with 2

-1 QRSS polynomials for T1/J1

- 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS or QRSS

error counter

- Analog loopback, Digital loopback, Remote loopback and Inband

loopback

Cable attenuation indication

Adaptive receive sensitivity

Non-intrusive monitoring per ITU G.772 specification

Short circuit protection and internal protection diode for line

drivers

LOS (Loss Of Signal) and AIS (Alarm Indication Signal) detection

JTAG interface

Supports serial control interface, Motorola and Intel Non-Multi-

plexed interfaces and hardware control mode

Pin compatible to 82V2042E T1/E1/J1 Short Haul LIU and

82V2052E E1 Short Haul LIU

Available in 80-pin TQFP and 81-pin FPBGA

Green package options available

DESCRIPTION:

The IDT82V2082 can be configured as a dual channel T1, E1 or J1 Line

Interface Unit. In receive path, an Adaptive Equalizer is integrated to

remove the distortion introduced by the cable attenuation. The IDT82V2082

also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and

detects and reports the LOS conditions. In transmit path, there is an AMI/

B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter

Attenuator, which can be placed in either the receive path or the transmit

path. The Jitter Attenuator can also be disabled. The IDT82V2082 supports

both Single Rail and Dual Rail system interfaces. To facilitate the network

maintenance, a PRBS/QRSS generation/detection circuit is integrated in

the chip, and different types of loopbacks can be set according to the appli-

cations. Four different kinds of line terminating impedance, 75

Ω,100 Ω,

110

Ω

and 120

Ω

are selectable on a per channel basis. The chip also pro-

vides driver short-circuit protection and internal protection diode and sup-

ports JTAG boundary scanning. The chip can be controlled by either

software or hardware.

The IDT82V2082 can be used in LAN, WAN, Routers, Wireless Base

Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,

CSU/DSU equipment, etc.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.



2009 Integrated Device Technology, Inc.

May 4, 2009

DSC-6229/7

Table of Contents

IDT82V2082 PIN CONFIGURATIONS .......................................................................................... 9

PIN DESCRIPTION ..................................................................................................................... 11

FUNCTIONAL DESCRIPTION .................................................................................................... 19

3.1

CONTROL MODE SELECTION ....................................................................................... 19

3.2

T1/E1/J1 MODE SELECTION .......................................................................................... 19

3.3

TRANSMIT PATH ............................................................................................................. 19

3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 19

3.3.2 ENCODER .............................................................................................................. 19

3.3.3 PULSE SHAPER .................................................................................................... 19

3.3.3.1 Preset Pulse Templates .......................................................................... 19

3.3.3.2 LBO (Line Build Out) ............................................................................... 20

3.3.3.3 User-Programmable Arbitrary Waveform ................................................ 21

3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 25

3.3.5 TRANSMIT PATH POWER DOWN ........................................................................ 26

3.4

RECEIVE PATH ............................................................................................................... 26

3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 26

3.4.2 LINE MONITOR ...................................................................................................... 27

3.4.3 ADAPTIVE EQUALIZER......................................................................................... 28

3.4.4 RECEIVE SENSITIVITY ......................................................................................... 28

3.4.5 DATA SLICER ........................................................................................................ 28

3.4.6 CDR (Clock & Data Recovery)................................................................................ 28

3.4.7 DECODER .............................................................................................................. 28

3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 28

3.4.9 RECEIVE PATH POWER DOWN........................................................................... 28

3.4.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 29

3.5

JITTER ATTENUATOR .................................................................................................... 30

3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 30

3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 30

3.6

LOS AND AIS DETECTION ............................................................................................. 31

3.6.1 LOS DETECTION ................................................................................................... 31

3.6.2 AIS DETECTION .................................................................................................... 34

3.7

TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 35

3.7.1 TRANSMIT ALL ONES ........................................................................................... 35

3.7.2 TRANSMIT ALL ZEROS......................................................................................... 35

3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 35

3.8

LOOPBACK ...................................................................................................................... 35

3.8.1 ANALOG LOOPBACK ............................................................................................ 35

May 4, 2009

Table of Contents

IDT82V2082

DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.16

3.8.2 DIGITAL LOOPBACK ............................................................................................. 35

3.8.3 REMOTE LOOPBACK............................................................................................ 36

3.8.4 INBAND LOOPBACK.............................................................................................. 37

3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 37

3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 37

3.8.4.3 Automatic Remote Loopback .................................................................. 38

ERROR DETECTION/COUNTING AND INSERTION ...................................................... 39

3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 39

3.9.2 ERROR DETECTION AND COUNTING ................................................................ 39

3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 40

LINE DRIVER FAILURE MONITORING ........................................................................... 40

MCLK AND TCLK ............................................................................................................. 41

3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 41

3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 41

MICROCONTROLLER INTERFACES ............................................................................. 42

3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 42

3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 42

INTERRUPT HANDLING .................................................................................................. 43

5V TOLERANT I/O PINS .................................................................................................. 44

RESET OPERATION ........................................................................................................ 44

POWER SUPPLY ............................................................................................................. 44

PROGRAMMING INFORMATION .............................................................................................. 45

4.1

4.2

Reserved Registers .......................................................................................................... 45

4.3

4.3.1 GLOBAL REGISTERS............................................................................................ 47

4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 48

4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 48

4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 49

4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 51

4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 53

4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 56

4.3.8 LINE STATUS REGISTERS ................................................................................... 59

4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 62

4.3.10 COUNTER REGISTERS ........................................................................................ 63

HARDWARE CONTROL PIN SUMMARY .................................................................................. 64

IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 66

6.1

JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 67

6.2

JTAG DATA REGISTER ................................................................................................... 67

6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 67

6.2.2 BYPASS REGISTER (BR)...................................................................................... 67

May 4, 2009

82V2082PF8 Related Products

	82V2082PF8	82V2082PFG8	82V2082PF
Description	PCM Transceiver, 1-Func, PQFP80, TQFP-80	PCM Transceiver, 1-Func, PQFP80, TQFP-80	PCM Transceiver, 1-Func, PQFP80, TQFP-80
Is it lead-free?	Contains lead	Lead free	Contains lead
Is it Rohs certified?	incompatible	conform to	incompatible
Parts packaging code	QFP	QFP	QFP
package instruction	LQFP, QFP80,.64SQ	LQFP, QFP80,.64SQ	TQFP-80
Contacts	80	80	80
Reach Compliance Code	_compli	compli	_compli
ECCN code	EAR99	EAR99	EAR99
JESD-30 code	S-PQFP-G80	S-PQFP-G80	S-PQFP-G80
JESD-609 code	e0	e3	e0
length	14 mm	14 mm	14 mm
Humidity sensitivity level	3	3	3
Number of functions	1	1	1
Number of terminals	80	80	80
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP
Encapsulate equivalent code	QFP80,.64SQ	QFP80,.64SQ	QFP80,.64SQ
Package shape	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240	260	240
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
Telecom integrated circuit types	PCM TRANSCEIVER	PCM TRANSCEIVER	PCM TRANSCEIVER
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Matte Tin (Sn) - annealed	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	20	30	20
width	14 mm	14 mm	14 mm
Base Number Matches	1	1	1
Maximum slew rate	0.18 mA	0.18 mA	-

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