GM72V28841AT/ALT
4Banks x 4M x 8Bit Synchronous DRAM
Description
The GM72V28841AT/ALT is a synchronous
dynamic random access memory comprised of
134,217,728 memory cells and logic including
input and output circuits operating synchronously
by referring to the positive edge of the externally
provided Clock.
The GM72V28841AT/ALT provides four
banks of 4,194,304 word by 8 bit to realize high
bandwidth with the Clock frequency up to 125
Mhz.
Pin Configuration
VCC
DQ0
VCCQ
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
VCC
NC
/WE
/CAS
/RAS
/CS
BA0/A13
BA1/A12
A10,AP
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Features
* PC100/PC66 Compatible
-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)
-10K(PC66)
* 3.3V single Power supply
* LVTTL interface
* Max Clock frequency
100/125 MHz
* 4,096 refresh cycle per 64 ms
* Two kinds of refresh operation
Auto refresh/ Self refresh
* Programmable burst access capability ;
- Sequence:Sequential / Interleave
- Length :1/2/4/8/FP
* Programmable CAS latency : 2/3
* 4 Banks can operate independently or
simultaneously
* Burst read/burst write or burst read/single
write operation capability
* Input and output masking by DQM input
* One Clock of back to back read or write
command interval
* Synchronous Power down and Clock
suspend capability with one Clock latency
for both entry and exit
* JEDEC Standard 54Pin 400mil TSOP II
Package
JEDEC STANDARD
400 mil 54 PIN TSOP II
(TOP VIEW)
VSS
DQ7
VSSQ
NC
DQ6
VCCQ
NC
DQ5
VSSQ
NC
DQ4
VCCQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Name
CLK
CKE
CS
RAS
CAS
WE
A0~A9,A11
A10 / AP
BA0/A13
~BA1/A12
DQ0~DQ7
DQM
VCCQ
VSSQ
VCC
VSS
NC
Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Address input or Auto Precharge
Bank select
Data input / Data output
Data input / output Mask
V
CC
for DQ
V
SS
for DQ
Power for internal circuit
Ground for internal circuit
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0/Dec.99
GM72V28841AT/ALT
Block Diagram
A0 to A13
A0 to A9
A0 to A13
Column address
counter
Column address
buffer
Row address
counter
Refresh
counter
Row decoder
Row decoder
Row decoder
Row decoder
Column decoder
Sense amplifier & I/O bus
Column decoder
Sense amplifier & I/O bus
Column decoder
Sense amplifier & I/O bus
Memory array
Bank 0
4096 row
x 1024 column
x 8 bit
Memory array
Bank 1
4096 row
x 1024 column
x 8 bit
Memory array
Bank 2
4096 row
x 1024 column
x 8 bit
Column decoder
Sense amplifier & I/O bus
Memory array
Bank 3
4096 row
x 1024 column
x 8 bit
Input
buffer
Output
buffer
Control logic &
timing generator
RAS
CAS
WE
CLK
Rev. 1.0/Dec.99
CKE
DQ0 to DQ7
DQM
CS
2
GM72V28841AT/ALT
Pin Description
Pin Name
CLK
(input pin)
CKE
(input pin)
DESCRIPTION
CLK is the master clock input to this pin. The other input signals are referred
at CLK rising edge.
This pin determines whether or not the next CLK is valid. If CKE is High, the
next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is
invalid. This pin is used for power-down and clock suspend modes.
When CS is Low, the command input cycle becomes valid. When CS is high,
all inputs are ignored. However, internal operations (bank active, burst
operations, etc.) are held.
Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read,
write, etc.) depending on the combination of their voltage levels. For details,
refer to the command operation section.
Row address (AX0 to AX11) is determined by A0 to A11 level at the bank
active command cycle CLK rising edge. Column address(AY0 to AY9;
GM72V28841AT/ALT) is determined by A0 to A9 level at the read or write
command cycle CLK rising edge. And this column address becomes burst
access start address. A10 defines the precharge mode. When A10 = High at
the precharge command cycle, all banks are precharged. But when A10 =
Low at the precharge command cycle, only the bank that is selected by
A12/A13 (BS) is precharged.
CS
(input pin)
RAS, CAS, and WE
(input pins)
A0 ~ A11
(input pins)
A12/A13
(input pin)
A12/A13 are bank select signal (BS). The memory array of the
GM72V28841AT/ALT is divided into bank 0, bank 1, bank2 and bank 3.
GM72V28841AT/ALT contain 4096-row x 1024-column x 8-bits. If A12 is
Low and if A13 is Low, bank 0 is selected. If A12 is High and A13 is Low,
bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12
is High and A13 is High, bank 3 is selected.
DQM, DQMU/DQML controls input/output buffers.
- Read operation: If DQM, DQMU/DQML is High, The output buffer
becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer
becomes Low-Z.
- Write operation: If DQM, DQMU/DQML is High, the previous data is held
(the new data is not written). If DQM, DQMU/DQML is Low, the data is
written.
DQM,
DQMU/DQML
(input pins)
Rev. 1.0/Dec.99
3
GM72V28841AT/ALT
Pin Description(Continued)
Pin Name
DQ0 ~ DQ3
(I/O pins)
V
CC
and V
CCQ
(power supply pins)
V
SS
and V
SSQ
(power supply pins)
NC
DESCRIPTION
Data is input and output from these pins. These pins are the same as those of a
conventional DRAM.
3.3 V is applied. (V
CC
is for the internal circuit and V
CCQ
is for the output
buffer.)
Ground is connected. (V
SS
is for the internal circuit and V
SSQ
is for the output
buffer.)
No Connection pins.
Command Operation
Command Truth Table
The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE
and address pins.
Function
Ignore command
No Operation
Burst stop in full page
Column address and
read command
Read with auto-precharge
Column address and
write command
Symbol
DESL
NOP
BST
READ
READ A
WRIT
CKE
n
n-1
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
V
X
CS
H
L
L
L
L
L
L
L
L
L
L
L
RAS
X
H
H
H
H
H
H
L
L
L
L
L
CAS
X
H
H
L
L
L
L
H
H
H
L
L
WE
X
H
L
H
H
L
L
H
L
L
H
L
A12~
A13
X
X
X
V
V
V
V
V
V
X
X
V
A10
X
X
X
L
H
L
H
V
L
H
X
V
A0~
A11
X
X
X
V
V
V
V
V
X
X
X
V
Write with auto-precharge WRIT A
Row address strobe and
bank active
Precharge select bank
Precharge all banks
Refresh
Mode register set
ACTV
PRE
PALL
REF/SELF
MRS
* Notes : H: V
IH
, L: V
IL
, X: V
IH
or V
IL
, V: Valid address
input
Rev. 1.0/Dec.99
4
GM72V28841AT/ALT
Ignore command [DESL]:
When this command
is set (CS is High), the synchronous DRAM
ignores command input at the clock. However, the
internal status is held.
No operation [NOP]:
This command is not an
execution command. However, the internal
operations continue.
Burst stop in full page [BST] :
This
command stops a full-page burst operation (burst
length = full-page(1024:GM72V28841AT/ALT),
and is illegal otherwise. Full page burst continues
until this command is input. When data
input/output is completed for full-page of data, it
automatically returns to the start address, and
input/output is performed repeatedly.
Column address strobe and read command
[READ]:
This command starts a read operation.
In addition, the start address of burst read is
determined by the column address
(AY0 to AY9:GM72V28841AT/ALT,) and the
bank select address (A12/A13). After the read
operation, the output buffer becomes High-Z.
Read with auto-precharge [READ A]:
This
command automatically performs a precharge
operation after a burst read with a burst length of
1, 2, 4 or 8. When the burst length is full-page,
this command is illegal.
Column address strobe and write command
[WRIT]:
This command starts a write operation.
When the burst write mode is selected, the column
address (AY0 to AY9; GM72V28841AT/ALT)
and the bank select address (A12/A13) become
the burst write start address. When the single write
mode is selected, data is only written to the
location specified by the column address (AY0 to
AY9; GM72V28841AT/ALT) and the bank select
address (A12/A13).
Write with auto-precharge [WRIT A]:
This
command automatically performs a precharge
operation after a burst write with a length of 1, 2,
4 or 8, or after a single write operation. When the
burst length is full-page, this command is illegal.
Row address strobe and bank activate
[ACTV]:
This command activates the bank that
is selected by A12/A13(BS) and determines the
row address (AX0 to AX11). If A12 is Low and
if A13 is Low, bank 0 is activated. If A12 is High
and A13 is Low, bank 1 is activated. If A12 is
Low and A13 is High, bank 2 is activated. If A12
is High and A13 is High, bank 3 is activated.
Precharge selected bank [PRE]:
This
command starts precharge operation for the bank
selected by A12/A13. If A12 is Low and if A13
is Low, bank 0 is selected. If A12 is High and
A13 is Low, bank 1 is selected. If A12 is Low
and A13 is High, bank 2 is selected. If A12 is
High and A13 is High, bank 3 is selected.
Precharge all banks [PALL]:
This command
starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the
refresh operation. There are two types of refresh
operation, the one is auto-refresh, and the other is
self-refresh. For details, refer to the CKE truth
table section.
Mode register set [MRS]:
Synchronous DRAM
has a mode register that defines how it operates.
The mode register is specified by the address pins
(A0 to A11) at the mode register set cycle. For
details, refer to the mode register configuration.
After power on, the contents of the mode register
are undefined, execute the mode register set
command to set up the mode register.
Rev. 1.0/Dec.99
5
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