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ADC08831/ADC08832 8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold
Function
September 1999
ADC08831/ADC08832
8-Bit Serial I/O CMOS A/D Converters with Multiplexer
and Sample/Hold Function
General Description
The ADC08831/ADC08832 are 8-bit successive approxima-
tion Analog to Digital converters with 3-wire serial interfaces
and a configurable input multiplexer for 2 channels. The se-
rial I/O will interface to COPS
™
family of micro-controllers,
PLD’s, microprocessors, DSP’s, or shift registers. The serial
I/O is configured to comply with the NSC MICROWIRE
™
se-
rial data exchange standard.
To
minimize
total
power
consumption,
the
ADC08831/ADC08832 automatically go into low power
mode whenever they are not performing conversions.
A track/hold function allows the analog voltage at the positive
input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various
combinations
of
single-ended,
differential,
or
pseudo-differential modes. The voltage reference input can
be adjusted to allow encoding of small analog voltage spans
to the full 8-bits of resolution.
n
Remote sensing in noisy environments
n
Instrumentation
n
Embedded Systems
Features
n
n
n
n
n
n
n
3-wire serial digital data link requires few I/O pins
Analog input track/hold function
2-channel input multiplexer option with address logic
Analog input voltage range from GND to V
CC
No zero or full scale adjustment required
TTL/CMOS input/output compatible
Superior pin compatible replacement for ADC0831/2
Key Specifications
n
n
n
n
n
n
n
Resolution: 8 bits
Conversion time (f
C
= 2 MHz): 4µs (max)
Power dissipation: 8.5mW (typ)
Low power mode: 3.0mW (typ)
Single supply: 5V
DC
Total unadjusted error:
±
1LSB
No missing codes over temperature
Applications
n
Digitizing sensors and waveforms
n
Process control monitoring
Typical Application
DS100108-44
DS100108-43
COPS
™
is a trademark of National Semiconductor Corporation.
MICROWIRE
™
is a trademark of National Semiconductor Corporation.
TRI-STATE
™
© 1999 National Semiconductor Corporation
DS100108
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Connection Diagrams
ADC08831
Wide Body SO Packages
ADC08832
Wide Body SO Packages
DS100108-4
DS100108-3
ADC08831
N,M,MM Packages
ADC08832
N,M,MM Packages
DS100108-2
DS100108-1
Ordering Information
Temperature Range
Industrial (−40˚C
≤
T
J
≤
+85˚C)
ADC08831IN
ADC08832IN
ADC08831IWM,
ADC08832IWM,
ADC08831IM,
ADC08832IM,
ADC08831IMM,
ADC08832IMM,
N08E
M14B
M08A
MUA08A
Package
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2
Absolute Maximum Ratings
(Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
ESD Susceptibility (Note 6)
Human Body Model
Machine Model
Junction Temperature (Note 5)
Storage Temperature Range
6.5V
−0.3V to V
CC
+ 0.3V
±
5 mA
±
20 mA
2000V
200V
150˚C
−65˚ C to 150˚C
Mounting Temperature
Lead Temp. (soldering, 10 sec)
Infrared (10 sec)
260˚C
215˚C
Operating Ratings
(Notes 2, 3)
Temperature Range
Supply Voltage
Thermal Resistance (θ
jA
)
SO Package, 8-pin Surface Mount
MSOP, 8-pin Surface Mount
SO Package, 14-pin Surface Mount
N Package, 8-pin
Clock Frequency
−40˚C
≤
T
J
≤
+85˚C
4.5 V to 6.0 V
190˚C/W
235˚C/W
145˚C/W
122˚C/W
10kHz≤f
CLK
≤2MHz
Electrical Characteristics
The following specifications apply for V
CC
= V
REF
= +5V
DC
, and f
CLK
= 2 MHz unless otherwise specified.
Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
LSB
(max)
LSB
LSB
LSB
LSB
2.8
5.9
(V
CC
+ 0.05)
(GND − 0.05)
kΩ (min)
kΩ (max)
V (max)
V (min)
LSB (max)
LSB (max)
LSB (max)
µA (max)
µA (min)
µA (min)
µA (max)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
TUE
Total Unadjusted Error
Offset Error
DNL
INL
FS
R
REF
V
IN
Differential NonLinearity
Integral NonLinearity
Full Scale Error
Reference Input Resistance
Analog Input Voltage
DC Common-Mode Error
Power Supply Sensitivity
On Channel Leakage Current
(Note 13)
V
CC
= 5V
±
10%,
V
CC
= 5V
±
5%
On Channel = 5V,
Off Channel = 0V
On Channel = 0V
Off Channel = 5V
On Channel = 5V,
Off Channel = 0V
On Channel = 0V,
Off Channel = 5V
(Note 11)
(Note 12)
(Note 10)
±
0.3
±
0.2
±
0.2
±
0.2
±
0.3
3.5
±
1
±
1
⁄
4
±
1
⁄
4
±
1
⁄
4
0.2
1
−0.2
−1
−0.2
−1
0.2
1
2.0
0.8
Off Channel Leakage Current
(Note 13)
DC CHARACTERISTICS
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Logical “1” Output Voltage
V
IN
= 5.0V
V
IN
= 0V
V
CC
= 4.75V:
I
OUT
= −360 µA
I
OUT
= −10 µA
V
OUT(0)
I
OUT
I
SOURCE
I
SINK
Logical “0” Output Voltage
TRI-STATE Output Current
Output Source Current
Output Sink Current
V
CC
= 4.75V
I
OUT
= 1.6 mA
V
OUT
= 0V
V
OUT
= 5V
V
OUT
= 0V
V
OUT
= V
CC
3
V (min)
V (max)
µA (max)
µA (max)
V (min)
V (min)
V (max)
µA (max)
µA (max)
mA (max)
mA (min)
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0.05
0.05
+1
−1
2.4
4.5
0.4
−3.0
3.0
−6.5
8.0
Electrical Characteristics
Symbol
Parameter
(Continued)
The following specifications apply for V
CC
= V
REF
= +5V
DC
, and f
CLK
= 2 MHz unless otherwise specified.
Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25˚C.
Conditions
Typical
(Note 8)
0.6
1.7
1.3
2.4
Limits
(Note 9)
1.0
2.4
1.8
3.5
Units
(Limits)
mA (max)
mA (max)
mA (max)
mA (max)
DC CHARACTERISTICS
I
CC
I
CC
Supply Current
CLK = V
CC
ADC08831
CS = V
CC
CS = LOW
CS = V
CC
CS = LOW
Supply Current ADC08832
CLK = V
CC
(Note 16)
Electrical Characteristics
The following specifications apply for V
CC
= V
REF
= +5 V
DC
, and t
r
= t
f
= 20 ns unless otherwise specified.
Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25˚C.
Symbol
f
CLK
Parameter
Clock Frequency
Clock Duty Cycle
(Note 14)
T
C
t
CA
t
SET-UP
t
HOLD
t
pd1
, t
pd0
Conversion Time (Not Including MUX
Addressing Time)
Acquisition Time
CS Falling Edge or Data Input
Valid to CLK Rising Edge
Data Input Valid after CLK
Rising Edge
CLK Falling Edge to Output
Data Valid (Note 15)
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
Capacitance of Analog Input (Note 17)
Capacitance of Logic Inputs
Capacitance of Logic Outputs
C
L
= 100 pF:
Data MSB First
Data LSB First
C
L
= 10 pF, R
L
= 10 kΩ
(see TRI-STATE Test Circuits)
C
L
= 100 pF, R
L
= 2 kΩ
f
CLK
= 2MHz
Conditions
Typical
(Note 8)
Limits
(Note 9)
2
40
60
8
4
12
Units
(Limits)
MHz (max)
% (min)
% (max)
1/f
CLK
(max)
µs (max)
1/f
CLK
(max)
ns (min)
ns (min)
⁄
25
20
250
200
50
180
13
5
5
ns (max)
ns (max)
ns
ns (max)
pF
pF
pF
t
1H
, t
0H
C
IN
C
IN
C
OUT
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