HY29F002
2 Megabit (256K x 16), 5 Volt-only, Flash Memory
KEY FEATURES
n
5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
n
High Performance
– Access times as fast as 45 ns
n
Low Power Consumption
– 20 mA typical active read current
– 30 mA typical program/erase current
– 1 µA typical CMOS standby current
n
Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n
Sector Erase Architecture
– Boot sector architecture with top and
bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and three 64K byte sectors
– A command can erase any combination of
sectors
– Supports full chip erase
n
Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F002 is an 2 Megabit, 5 volt-only CMOS
Flash memory organized as 262,144 (256K) bytes.
The device is offered in industry-standard 32-pin
PDIP, TSOP and PLCC packages.
The HY29F002 can be programmed and erased
in-system with a single 5-volt V
CC
supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 55ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
A 45ns version operating over 5.0 volts ± 5% is
also available. To eliminate bus contention, the
18
A[17:0]
RESET#
CE#
OE#
WE#
DQ[7:0]
8
n
Sector Protection
– Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
n
Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n
Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n
Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n
Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 7 sec typical
n
Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n
Minimum 100,000 Program/Erase Cycles
n
Space Efficient Packaging
– Available in industry-standard 32-pin
PDIP, TSOP and PLCC packages
LOGIC DIAGRAM
Preliminary
Revision 4, January 2000
HY29F002
HY29F002 has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte at a time
by executing the four-cycle Program Command.
This initiates an internal algorithm that automati-
cally times the program pulse widths and verifies
proper cell margin.
The HY29F002’s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
device while it is in the system (e.g., by a virus),
BLOCK DIAGRAM
DQ[7:0]
the device has a Sector Protect function which
hardware write protects selected sectors. The
sector protect and unprotect features can be en-
abled in a PROM programmer. Temporary Sec-
tor Unprotect, which requires a high voltage, al-
lows in-system erasure and code changes in pre-
viously protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
reading the DQ[7] (Data# Polling) and DQ[6]
(toggle) status bits. Reading data from the device
is similar to reading from SRAM or EPROM de-
vices. Hardware data protection measures include
a low V
CC
detector that automatically inhibits write
operations during power transitions.
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
STATE
CONTROL
DQ[7:0]
WE#
CE#
OE#
RESET#
ELECTRONIC
ID
COMMAND
REGISTER
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
I/O BUFFERS
DATA LATCH
PROGRAM
VOLTAGE
GENERATOR
Y-DECODER
Y-GATING
2 MBIT
FLASH
MEMORY
ARRAY
(7 Sectors)
V
SS
V
CC
A[17:0]
V
CC
DETECTOR
TIMER
ADDRESS LATCH
X-DECODER
2
Rev. 4.0/Jan. 00
HY29F002
PIN CONFIGURATIONS
RESET#
A[16]
A[15]
A[12]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
DQ[0]
DQ[1]
DQ[2]
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
A[17]
A[14]
A[13]
A[8]
A[9]
A[11]
OE#
A[10]
CE#
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
A[11]
A[9]
A[8]
A[13]
A[14]
A[17]
WE#
V
CC
RESET#
A[16]
A[15]
A[12]
A[7]
A[6]
A[5]
A[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A[10]
CE#
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
V
SS
DQ[2]
DQ[1]
DQ[0]
A[0]
A[1]
A[2]
A[3]
PDIP32
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
DQ[0]
5
6
7
8
9
10
11
12
13
A[12]
A[15]
A[16]
RESET#
V
CC
WE#
A[17]
4 3 2 1 32 31 30
29
28
27
26
25
24
23
22
21
A[14]
A[13]
A[8]
A[9]
A[11]
OE#
A[10]
CE#
DQ[7]
PLCC32
14 15 16 17 18 19 20
DQ[1]
DQ[2]
V
SS
DQ[3]
DQ[4]
DQ[5]
DQ[6]
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the sig-
nal is asserted in a Low state (nominally 0 volts).
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexa-
decimal notation. The designation 0bXXXX indi-
cates a number expressed in binary notation (X =
0, 1).
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Rev. 4.0/Jan. 00
HY29F002
SIGNAL DESCRIPTIONS
Name
A[17:0]
DQ[7:0]
CE#
Type
Inputs
Description
Address, active High.
These eighteen inputs select one of 262,144 (256K)
bytes within the array for read or write operations. A[17] is the MSB and A[0]
is the LSB.
Inputs/Outputs
Data Bus, active High
. These pins provide an 8-bit data path for read and write
Tri-state
operations.
Input
Chip Enable, active Low.
This input must be asserted to read data from or
write data to the HY 29F002. When High, the data bus is tri-stated and the device
is placed in the Standby mode.
Output Enable, active Low
. This input must be asserted for read operations
and negated for write operations. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
W r it e E n a b le , a c t iv e L o w.
Co nt r o ls w r it ing o f c o mma nd s o r c o mma nd
sequences in or der t o pr ogr am dat a or per f or m ot her oper at ions. A w r it e
operation takes place when WE# is asserted while CE# is Low and OE# is High.
Hardware Reset, active Low.
Provides a hardware method of resetting the
HY 29F002 to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
5-volt power supply.
Power and signal ground.
OE#
Input
WE#
Input
RESET#
Input
V
CC
V
SS
--
--
MEMORY ARRAY ORGANIZATION
The 256 Kbyte Flash memory array is organized
into seven blocks called
sectors
(S0, S1, . . . ,
S6). A sector is the smallest unit that can be
erased and which can be protected to prevent
accidental or unauthorized erasure. See the ‘Bus
Operations’ and ‘Command Definitions’ sections
of this document for additional information on these
functions.
In the HY29F002, four of the sectors, which com-
prise the
boot block,
vary in size from 8 to 32
Kbytes, while the remaining three sectors are
uniformly sized at 64 Kbytes. The boot block can
be located at the bottom of the address range
(HY29F002B) or at the top of the address range
(HY29F002T).
Table 1 defines the sector addresses and corre-
sponding address ranges for the top and bottom
boot block versions of the HY29F002.
4
Rev. 4.0/Jan. 00
HY29F002
Table 1. HY29F002 Memory Array Organization
Device
Sector
S0
S1
S2
S3
S4
S5
S6
S0
S1
S2
S3
S4
S5
S6
Size
(Kbytes)
64
64
64
32
8
8
16
16
8
8
32
64
64
64
Sector Address
Address Range
A[13]
X
X
X
X
0
1
X
X
0
1
X
X
X
X
0x00000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x39FFF
0x3A000 - 0x3BFFF
0x3C000 - 0x3FFFF
0x00000 - 0x03FFF
0x04000 - 0x05FFF
0x06000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x3FFFF
A[17]
0
0
1
1
1
1
1
0
0
0
0
0
1
1
A[16]
0
1
0
1
1
1
1
0
0
0
0
1
0
1
A[15]
X
X
X
0
1
1
1
0
0
0
1
X
X
X
A[14]
X
X
X
X
0
0
1
0
1
1
X
X
X
X
Top
Boot Sector
HY29F002T
Bottom
Boot Sector
HY29F002B
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
Table 2. HY29F002 Normal Bus Operations
1
Operation
Read
Write
Output Disable
CE# TTL Standby
CE# CMOS Standby
Hardware Reset (TTL Standby)
Hardware Reset (CMOS Standby)
CE#
L
L
L
H
V
CC
± 0.5V
X
X
OE#
L
H
H
X
X
X
X
WE#
H
L
H
X
X
X
X
RESET #
H
H
H
H
V
CC
± 0.5V
L
V
SS
± 0.5V
A[17:0]
A
IN
A
IN
X
X
X
X
X
DQ[7:0]
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
High-Z
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Read Operation
Data is read from the HY29F002 by using stan-
dard microprocessor read cycles while placing the
address of the byte to be read on the device’s
address inputs, A[17:0]. As shown in Table 2, the
host system must drive the CE# and OE# inputs
Notes:
1. L = V
IL
, H = V
IH
, X = Don’t Care, D
OUT
= Data Out, D
IN
= Data In. See DC Characteristics for voltage levels.
Rev. 4.0/Jan. 00
5
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