DS31256 datasheet, PDF - EEWORLD Datasheet

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DS31256: DescriptionMicro Peripheral IC,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，181 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

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Maker	DALLAS
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DEMO KIT AVAILABLE

DS31256 Envoy

256-Channel, High-Throughput

HDLC Controller

www.maxim-ic.com

GENERAL DESCRIPTION

The DS31256 Envoy is a 256-channel HDLC

controller capable of handling up to 64 T1 or E1

data streams or two T3 data streams. Each of the

16 physical ports can handle one, two, or four

T1 or E1 data streams. The Envoy is composed

of the following blocks: Layer 1, HDLC

processing, FIFO, DMA, PCI bus, and local bus.

There are 16 HDLC engines (one for each port)

that are each capable of operating at speeds up

to 8.192Mbps in channelized mode and up to

10Mbps in unchannelized mode. The Envoy also

has three fast HDLC engines that only reside on

Ports 0, 1, and 2. They are capable of operating

at speeds up to 52Mbps.

FEATURES

256 Independent, Bidirectional HDLC

channels

Up to 132Mbps Full-Duplex Throughput

Supports Up to 64 T1 or E1 Data Streams

16 Physical Ports (16 Tx and 16 Rx) That

Can Be Independently Configured for

Channelized or Unchannelized Operation

Three Fast (52Mbps) Ports; Other Ports

Capable of Speeds Up to 10Mbps

(Unchannelized)

Channelized Ports Can Each Handle One,

Two, or Four T1 or E1 Lines

Per-Channel DS0 Loopbacks in Both

Directions

Over-Subscription at the Port Level

Transparent Mode Supported

On-Board Bit Error-Rate Tester (BERT)

with Automatic Error Insertion Capability

BERT function Can Be Assigned to Any

HDLC Channel or Any Port

Large 16kB FIFO in Both Receive and

Transmit Directions

Efficient Scatter/Gather DMA Maximizes

Memory Efficiency

Receive Data Packets are Time-Stamped

Transmit Packet Priority Setting

V.54 Loopback Code Detector

Local Bus Allows for PCI Bridging or Local

Access

Intel or Motorola Bus Signals Supported

Backward Compatibility with DS3134

33MHz 32-Bit PCI (V2.1) Interface

3.3V Low-Power CMOS with 5V Tolerant

I/O

JTAG Support IEEE 1149.1

256-Pin Plastic BGA (27mm x 27mm)

Features continued on page 6.

APPLICATIONS

Channelized and Clear-Channel

(Unchannelized) T1/E1 and T3/E3

Routers with Multilink PPP Support

High-Density Frame-Relay Access

xDSL Access Multiplexers (DSLAMs)

Triple HSSI

High-Density V.35

SONET/SDH EOC/ECC Termination

ORDERING INFORMATION

PART

DS31256

TEMP RANGE

0°C to +70°C

PIN-PACKAGE

256 PBGA

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

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112102

DS31256

LIST OF FIGURES

Figure 2-1. Block Diagram ....................................................................................................................................... 10

Figure 5-1. Status Register Block Diagram for SM and SV54................................................................................. 36

Figure 6-1. Layer 1 Block Diagram.......................................................................................................................... 46

Figure 6-2. Port Timing (Channelized and Unchannelized Applications) ............................................................... 47

Figure 6-3. Layer 1 Register Set............................................................................................................................... 51

Figure 6-4. Port RAM Indirect Access ..................................................................................................................... 53

Figure 6-5. Receive V.54 Host Algorithm................................................................................................................ 58

Figure 6-6. Receive V.54 State Machine.................................................................................................................. 59

Figure 6-7. BERT Mux Diagram.............................................................................................................................. 60

Figure 6-8. BERT Register Set................................................................................................................................. 61

Figure 8-1. FIFO Example........................................................................................................................................ 75

Figure 9-1. Receive DMA Operation ....................................................................................................................... 88

Figure 9-2. Receive DMA Memory Organization.................................................................................................... 89

Figure 9-3. Receive Descriptor Example.................................................................................................................. 90

Figure 9-4. Receive Packet Descriptors.................................................................................................................... 91

Figure 9-5. Receive Free-Queue Descriptor ............................................................................................................. 92

Figure 9-6. Receive Free-Queue Structure ............................................................................................................... 94

Figure 9-7. Receive Done-Queue Descriptor ........................................................................................................... 97

Figure 9-8. Receive Done-Queue Structure.............................................................................................................. 99

Figure 9-9. Receive DMA Configuration RAM..................................................................................................... 102

Figure 9-10. Transmit DMA Operation.................................................................................................................. 108

Figure 9-11. Transmit DMA Memory Organization .............................................................................................. 109

Figure 9-12. Transmit DMA Packet Handling ....................................................................................................... 110

Figure 9-13. Transmit DMA Priority Packet Handling .......................................................................................... 111

Figure 9-14. Transmit DMA Error Recovery Algorithm ....................................................................................... 113

Figure 9-15. Transmit Descriptor Example ............................................................................................................ 114

Figure 9-16. Transmit Packet Descriptors .............................................................................................................. 115

Figure 9-17. Transmit Pending-Queue Descriptor ................................................................................................. 116

Figure 9-18. Transmit Pending-Queue Structure.................................................................................................... 118

Figure 9-19. Transmit Done-Queue Descriptor...................................................................................................... 120

Figure 9-20. Transmit Done-Queue Structure ........................................................................................................ 122

Figure 9-21. Transmit DMA Configuration RAM ................................................................................................. 125

Figure 10-1. PCI Configuration Memory Map....................................................................................................... 130

Figure 10-2. PCI Bus Read..................................................................................................................................... 131

Figure 10-3. PCI Bus Write.................................................................................................................................... 132

Figure 10-4. PCI Bus Arbitration Signaling Protocol............................................................................................. 133

Figure 10-5. PCI Initiator Abort ............................................................................................................................. 133

Figure 10-6. PCI Target Retry................................................................................................................................ 134

Figure 10-7. PCI Target Disconnect....................................................................................................................... 134

Figure 10-8. PCI Target Abort................................................................................................................................ 135

Figure 10-9. PCI Fast Back-To-Back ..................................................................................................................... 136

Figure 11-1. Bridge Mode ...................................................................................................................................... 148

Figure 11-2. Bridge Mode With Arbitration Enabled............................................................................................. 148

Figure 11-3. Configuration Mode........................................................................................................................... 149

Figure 11-4. Local Bus Access Flowchart.............................................................................................................. 152

Figure 11-5. 8-Bit Read Cycle................................................................................................................................ 155

Figure 11-6. 16-Bit Write Cycle............................................................................................................................. 156

Figure 11-7. 8-Bit Read Cycle................................................................................................................................ 157

Figure 11-8. 16-Bit Write (Only Upper 8-Bits Active) Cycle ................................................................................ 158

Figure 11-9. 8-Bit Read Cycle................................................................................................................................ 159

Figure 11-10. 8-Bit Write Cycle............................................................................................................................. 160

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DS31256

Figure 11-11. 16-Bit Read Cycle............................................................................................................................ 161

Figure 11-12. 8-Bit Write Cycle............................................................................................................................. 162

Figure 12-1. Block Diagram ................................................................................................................................... 163

Figure 12-2. TAP Controller State Machine........................................................................................................... 164

Figure 13-1. Layer 1 Port AC Timing Diagram ..................................................................................................... 169

Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram................................................................. 170

Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams.................................................... 172

Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (Continued) ............................... 173

Figure 13-5. PCI Bus Interface AC Timing Diagram............................................................................................. 174

Figure 13-6. JTAG Test Port Interface AC Timing Diagram................................................................................. 175

Figure 15-1. Application Drawing Key .................................................................................................................. 177

Figure 15-2. Single T1/E1 Line Connection........................................................................................................... 177

Figure 15-3. Quad T1/E1 Connection .................................................................................................................... 178

Figure 15-4. 16-Port T1 Application ...................................................................................................................... 178

Figure 15-5. Dual T3 Application .......................................................................................................................... 179

Figure 15-6. T3 Application (512 HDLC Channels).............................................................................................. 180

Figure 15-7. T3 Application (672 HDLC Channels).............................................................................................. 181

LIST OF TABLES

Table 1-A. Data Sheet Definitions.............................................................................................................................. 7

Table 2-A. Restrictions for Rev B1/B2 Silicon ........................................................................................................ 11

Table 2-B. Initialization Steps .................................................................................................................................. 12

Table 2-C. Indirect Registers.................................................................................................................................... 12

Table 3-A. Signal Description .................................................................................................................................. 13

Table 3-B. RS Sampled Edge ................................................................................................................................... 18

Table 3-C. TS Sampled Edge ................................................................................................................................... 19

Table 4-A. Memory Map Organization .................................................................................................................... 26

Table 6-A. Channelized Port Modes ........................................................................................................................ 44

Table 6-B. Receive V.54 Search Routine................................................................................................................. 57

Table 7-A. Receive HDLC Packet Processing Outcomes ........................................................................................ 67

Table 7-B. Receive HDLC Functions....................................................................................................................... 68

Table 7-C. Transmit HDLC Functions ..................................................................................................................... 68

Table 8-A. FIFO Priority Algorithm Select.............................................................................................................. 74

Table 9-A. DMA Registers to be Configured by the Host on Power-Up ................................................................. 84

Table 9-B. Receive DMA Main Operational Areas ................................................................................................. 86

Table 9-C. Receive Descriptor Address Storage ...................................................................................................... 90

Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation............................................... 93

Table 9-E. Receive Free-Queue Internal Address Storage ....................................................................................... 93

Table 9-F. Receive Done-Queue Internal Address Storage...................................................................................... 98

Table 9-G. Transmit DMA Main Operational Areas.............................................................................................. 106

Table 9-H. Done-Queue Error-Status Conditions................................................................................................... 112

Table 9-I. Transmit Descriptor Address Storage .................................................................................................... 114

Table 9-J. Transmit Pending-Queue Internal Address Storage .............................................................................. 117

Table 9-K. Transmit Done-Queue Internal Address Storage ................................................................................. 121

Table 11-A. Local Bus Signals............................................................................................................................... 147

Table 11-B. Local Bus 8-Bit Width Address,

LBHE

Setting ................................................................................. 150

Table 11-C. Local Bus 16-Bit Width Address, Ld,

LBHE

Setting......................................................................... 150

Table 12-A. Instruction Codes................................................................................................................................ 166

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