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DEMO KIT AVAILABLE
DS31256
256-Channel, High-Throughput
HDLC Controller
www.maxim-ic.com
GENERAL DESCRIPTION
The DS31256 Envoy is a 256-channel HDLC
controller that can handle up to 60 T1 or 64 E1
data streams or two T3 data streams. Each of the
16 physical ports can handle one, two, or four
T1 or E1 data streams. The DS31256 is
composed of the following blocks: Layer 1,
HDLC processing, FIFO, DMA, PCI bus, and
local bus.
There are 16 HDLC engines (one for each port)
that are each capable of operating at speeds up
to 8.192Mbps in channelized mode and up to
10Mbps in unchannelized mode. The DS31256
Envoy also has three fast HDLC engines that
only reside on Ports 0, 1, and 2. They are
capable of operating at speeds up to 52Mbps.
FEATURES
256 Independent, Bidirectional HDLC
Channels
Up to 132Mbps Full-Duplex Throughput
Supports Up to 60 T1 or 64 E1 Data Streams
16 Physical Ports (16 Tx and 16 Rx) That
Can Be Independently Configured for
Channelized or Unchannelized Operation
Three Fast (52Mbps) Ports; Other Ports
Capable of Speeds Up to 10Mbps
(Unchannelized)
Channelized Ports Can Each Handle One,
Two, or Four T1 or E1 Lines
Per-Channel DS0 Loopbacks in Both
Directions
Over-Subscription at the Port Level
Transparent Mode Supported
On-Board Bit Error-Rate Tester (BERT)
with Automatic Error Insertion Capability
BERT Function Can Be Assigned to Any
HDLC Channel or Any Port
Large 16kB FIFO in Both Receive and
Transmit Directions
Efficient Scatter/Gather DMA Maximizes
Memory Efficiency
Receive Data Packets are Time-Stamped
Transmit Packet Priority Setting
V.54 Loopback Code Detector
Local Bus Allows for PCI Bridging or Local
Access
Intel or Motorola Bus Signals Supported
Backward Compatibility with DS3134
33MHz 32-Bit PCI (V2.1) Interface
3.3V Low-Power CMOS with 5V Tolerant
I/O
JTAG Support IEEE 1149.1
256-Pin Plastic BGA (27mm x 27mm)
Features continued on page 6.
APPLICATIONS
Channelized and Clear-Channel
(Unchannelized) T1/E1 and T3/E3
Routers with Multilink PPP Support
High-Density Frame-Relay Access
xDSL Access Multiplexers (DSLAMs)
Triple HSSI
High-Density V.35
SONET/SDH EOC/ECC Termination
ORDERING INFORMATION
PART
DS31256
DS31256+
TEMP RANGE
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
256 PBGA
256 PBGA
+
Denotes lead-free/RoHS-compliant package.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1 of 183
REV: 012506
DS31256 256-Channel, High-Throughput HDLC Controller
TABLE OF CONTENTS
1.
2.
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
MAIN FEATURES............................................................................................................6
DETAILED DESCRIPTION ..............................................................................................7
SIGNAL DESCRIPTION ................................................................................................13
O
VERVIEW
/S
IGNAL
L
IST
.............................................................................................................13
S
ERIAL
P
ORT
I
NTERFACE
S
IGNAL
D
ESCRIPTION
..........................................................................18
L
OCAL
B
US
S
IGNAL
D
ESCRIPTION
..............................................................................................19
JTAG S
IGNAL
D
ESCRIPTION
......................................................................................................22
PCI B
US
S
IGNAL
D
ESCRIPTION
..................................................................................................22
PCI E
XTENSION
S
IGNALS
...........................................................................................................25
S
UPPLY AND
T
EST
S
IGNAL
D
ESCRIPTION
....................................................................................25
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
MEMORY MAP ..............................................................................................................26
I
NTRODUCTION
..........................................................................................................................26
G
ENERAL
C
ONFIGURATION
R
EGISTERS
(0
XX
) .............................................................................26
R
ECEIVE
P
ORT
R
EGISTERS
(1
XX
)...............................................................................................27
T
RANSMIT
P
ORT
R
EGISTERS
(2
XX
).............................................................................................27
C
HANNELIZED
P
ORT
R
EGISTERS
(3
XX
) .......................................................................................28
HDLC R
EGISTERS
(4
XX
)............................................................................................................29
BERT R
EGISTERS
(5
XX
)............................................................................................................29
R
ECEIVE
DMA R
EGISTERS
(7
XX
) ...............................................................................................29
T
RANSMIT
DMA R
EGISTERS
(8
XX
) .............................................................................................30
FIFO R
EGISTERS
(9
XX
) .............................................................................................................30
PCI C
ONFIGURATION
R
EGISTERS FOR
F
UNCTION
0 (PIDSEL/A
XX
).............................................31
PCI C
ONFIGURATION
R
EGISTERS FOR
F
UNCTION
1 (PIDSEL/B
XX
).............................................31
5.
5.1
5.2
5.3
GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT...........................32
M
ASTER
R
ESET AND
ID R
EGISTER
D
ESCRIPTION
........................................................................32
M
ASTER
C
ONFIGURATION
R
EGISTER
D
ESCRIPTION
....................................................................32
S
TATUS AND
I
NTERRUPT
............................................................................................................34
General Description of Operation ....................................................................................................... 34
Status and Interrupt Register Description ........................................................................................... 37
5.3.1
5.3.2
5.4
T
EST
R
EGISTER
D
ESCRIPTION
...................................................................................................43
6.
6.1
6.2
6.3
6.4
6.5
6.6
LAYER 1 ........................................................................................................................44
G
ENERAL
D
ESCRIPTION
.............................................................................................................44
P
ORT
R
EGISTER
D
ESCRIPTIONS
.................................................................................................48
L
AYER
1 C
ONFIGURATION
R
EGISTER
D
ESCRIPTION
....................................................................51
R
ECEIVE
V.54 D
ETECTOR
..........................................................................................................56
BERT .......................................................................................................................................60
BERT R
EGISTER
D
ESCRIPTION
.................................................................................................61
7.
7.1
7.2
HDLC .............................................................................................................................67
G
ENERAL
D
ESCRIPTION
.............................................................................................................67
HDLC R
EGISTER
D
ESCRIPTION
.................................................................................................69
8.
8.1
FIFO ...............................................................................................................................74
G
ENERAL
D
ESCRIPTION AND
E
XAMPLE
.......................................................................................74
Receive High Watermark .................................................................................................................... 76
Transmit Low Watermark .................................................................................................................... 76
8.1.1
8.1.2
8.2
FIFO R
EGISTER
D
ESCRIPTION
...................................................................................................76
9.
9.1
9.2
DMA ...............................................................................................................................83
I
NTRODUCTION
..........................................................................................................................83
R
ECEIVE
S
IDE
...........................................................................................................................85
Overview ............................................................................................................................................. 85
Packet Descriptors .............................................................................................................................. 90
Free Queue ......................................................................................................................................... 92
Done Queue........................................................................................................................................ 97
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9.2.1
9.2.2
9.2.3
9.2.4
DS31256 256-Channel, High-Throughput HDLC Controller
9.2.5
DMA Channel Configuration RAM .................................................................................................... 102
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
T
RANSMIT
S
IDE
.......................................................................................................................105
Overview ........................................................................................................................................... 105
Packet Descriptors ............................................................................................................................ 114
Pending Queue ................................................................................................................................. 116
Done Queue...................................................................................................................................... 120
DMA Configuration RAM................................................................................................................... 125
10.
10.1
PCI BUS.......................................................................................................................130
G
ENERAL
D
ESCRIPTION OF
O
PERATION
...................................................................................130
PCI Read Cycle................................................................................................................................. 131
PCI Write Cycle................................................................................................................................. 132
PCI Bus Arbitration............................................................................................................................ 133
PCI Initiator Abort.............................................................................................................................. 133
PCI Target Retry ............................................................................................................................... 134
PCI Target Disconnect ...................................................................................................................... 134
PCI Target Abort ............................................................................................................................... 135
PCI Fast Back-to-Back...................................................................................................................... 136
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.1.7
10.1.8
10.2
10.2.1
10.2.2
10.2.3
10.2.4
PCI C
ONFIGURATION
R
EGISTER
D
ESCRIPTION
.........................................................................137
Command Bits (PCMD0)................................................................................................................... 138
Status Bits (PCMD0) ......................................................................................................................... 139
Command Bits (PCMD1)................................................................................................................... 143
Status Bits (PCMD1) ......................................................................................................................... 144
11.
11.1
LOCAL BUS ................................................................................................................147
G
ENERAL
D
ESCRIPTION
...........................................................................................................147
PCI Bridge Mode............................................................................................................................... 149
Configuration Mode........................................................................................................................... 151
11.1.1
11.1.2
11.2
11.3
L
OCAL
B
US
B
RIDGE
M
ODE
C
ONTROL
R
EGISTER
D
ESCRIPTION
..................................................153
E
XAMPLES OF
B
US
T
IMING FOR
L
OCAL
B
US
PCI B
RIDGE
M
ODE
O
PERATION
.............................155
12.
12.1
12.2
12.3
12.4
JTAG............................................................................................................................163
JTAG D
ESCRIPTION
................................................................................................................163
TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
...................................................................164
I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
............................................................................166
T
EST
R
EGISTERS
.....................................................................................................................167
13.
14.
15.
15.1
AC CHARACTERISTICS .............................................................................................168
REVISION HISTORY ...................................................................................................176
PACKAGE INFORMATION .........................................................................................177
256-
PIN
PBGA (27
MM X
27
MM
) ...............................................................................................177
16.
17.
17.1
17.2
17.3
17.4
THERMAL CHARACTERISTICS.................................................................................178
APPLICATIONS...........................................................................................................179
16 P
ORT
T1
OR
E1
WITH
256 HDLC C
HANNEL
S
UPPORT
.........................................................180
D
UAL
T3
WITH
256 HDLC C
HANNEL
S
UPPORT
........................................................................181
S
INGLE
T3
WITH
512 HDLC C
HANNEL
S
UPPORT
......................................................................182
S
INGLE
T3
WITH
672 HDLC C
HANNEL
S
UPPORT
......................................................................183
3 of 183
DS31256 256-Channel, High-Throughput HDLC Controller
LIST OF FIGURES
Figure 2-1. Block Diagram .......................................................................................................................10
Figure 5-1. Status Register Block Diagram for SM and SV54 .................................................................36
Figure 6-1. Layer 1 Block Diagram ..........................................................................................................46
Figure 6-2. Port Timing (Channelized and Unchannelized Applications) ................................................47
Figure 6-3. Layer 1 Register Set .............................................................................................................51
Figure 6-4. Port RAM Indirect Access .....................................................................................................53
Figure 6-5. Receive V.54 Host Algorithm ................................................................................................58
Figure 6-6. Receive V.54 State Machine .................................................................................................59
Figure 6-7. BERT Mux Diagram ..............................................................................................................60
Figure 6-8. BERT Register Set ................................................................................................................61
Figure 8-1. FIFO Example .......................................................................................................................75
Figure 9-1. Receive DMA Operation........................................................................................................88
Figure 9-2. Receive DMA Memory Organization .....................................................................................89
Figure 9-3. Receive Descriptor Example .................................................................................................90
Figure 9-4. Receive Packet Descriptors ..................................................................................................91
Figure 9-5. Receive Free-Queue Descriptor............................................................................................92
Figure 9-6. Receive Free-Queue Structure .............................................................................................94
Figure 9-7. Receive Done-Queue Descriptor ..........................................................................................97
Figure 9-8. Receive Done-Queue Structure ............................................................................................99
Figure 9-9. Receive DMA Configuration RAM .......................................................................................102
Figure 9-10. Transmit DMA Operation...................................................................................................108
Figure 9-11. Transmit DMA Memory Organization ................................................................................109
Figure 9-12. Transmit DMA Packet Handling ........................................................................................110
Figure 9-13. Transmit DMA Priority Packet Handling ............................................................................111
Figure 9-14. Transmit DMA Error Recovery Algorithm ..........................................................................113
Figure 9-15. Transmit Descriptor Example ............................................................................................114
Figure 9-16. Transmit Packet Descriptors .............................................................................................115
Figure 9-17. Transmit Pending-Queue Descriptor.................................................................................116
Figure 9-18. Transmit Pending-Queue Structure...................................................................................118
Figure 9-19. Transmit Done-Queue Descriptor .....................................................................................120
Figure 9-20. Transmit Done-Queue Structure .......................................................................................122
Figure 9-21. Transmit DMA Configuration RAM ....................................................................................125
Figure 10-1. PCI Configuration Memory Map ........................................................................................130
Figure 10-2. PCI Bus Read ...................................................................................................................131
Figure 10-3. PCI Bus Write....................................................................................................................132
Figure 10-4. PCI Bus Arbitration Signaling Protocol..............................................................................133
Figure 10-5. PCI Initiator Abort ..............................................................................................................133
Figure 10-6. PCI Target Retry ...............................................................................................................134
Figure 10-7. PCI Target Disconnect ......................................................................................................134
Figure 10-8. PCI Target Abort ...............................................................................................................135
Figure 10-9. PCI Fast Back-To-Back.....................................................................................................136
Figure 11-1. Bridge Mode ......................................................................................................................148
Figure 11-2. Bridge Mode with Arbitration Enabled ...............................................................................148
Figure 11-3. Configuration Mode ...........................................................................................................149
Figure 11-4. Local Bus Access Flowchart .............................................................................................152
Figure 11-5. 8-Bit Read Cycle ...............................................................................................................155
Figure 11-6. 16-Bit Write Cycle..............................................................................................................156
Figure 11-7. 8-Bit Read Cycle ...............................................................................................................157
Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle ...................................................................158
Figure 11-9. 8-Bit Read Cycle ...............................................................................................................159
Figure 11-10. 8-Bit Write Cycle..............................................................................................................160
Figure 11-11. 16-Bit Read Cycle ...........................................................................................................161
4 of 183
Microcontroller MCU
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