DS33ZH11 datasheet, PDF - EEWORLD Datasheet

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DS33ZH11: DescriptionDATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100, 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100; CategoryWireless rf/communication Telecom circuit; File Size2MB，173 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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DS33ZH11 Overview

DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100, 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100

DS33ZH11 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Rochester Electronics
Parts packaging code	BGA
package instruction	10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
Contacts	100
Reach Compliance Code	unknown
JESD-30 code	S-PBGA-B100
JESD-609 code	e0
length	10 mm
Humidity sensitivity level	NOT SPECIFIED
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Package shape	SQUARE
Package form	GRID ARRAY, FINE PITCH
Peak Reflow Temperature (Celsius)	225
Certification status	COMMERCIAL
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	SUPPORT CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

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DS33Z11 Ethernet Mapper

TABLE OF CONTENTS

DESCRIPTION..................................................................................................................................7

FEATURE HIGHLIGHTS ..................................................................................................................8

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

ENERAL

.......................................................................................................................................................8

ERIAL

NTERFACE

.........................................................................................................................................8

HDLC ...........................................................................................................................................................8

OMMITTED

NFORMATION

ATE

(CIR) C

ONTROLLER

......................................................................................8

X.86 S

UPPORT

..............................................................................................................................................8

SDRAM I

NTERFACE

.......................................................................................................................................9

MAC I

NTERFACE

............................................................................................................................................9

ICROPROCESSOR

NTERFACE

.......................................................................................................................9

ERIAL

SPI I

NTERFACE

—M

ASTER

ODE

NLY

...............................................................................................9

EFAULT

ONFIGURATIONS

............................................................................................................................9

EST AND

IAGNOSTICS

.................................................................................................................................9

PECIFICATIONS

OMPLIANCE

......................................................................................................................10

APPLICATIONS .............................................................................................................................11

ACRONYMS AND GLOSSARY .....................................................................................................14

MAJOR OPERATING MODES.......................................................................................................15

BLOCK DIAGRAMS.......................................................................................................................16

PIN DESCRIPTIONS ......................................................................................................................17

7.1

UNCTIONAL

ESCRIPTION

.....................................................................................................................17

FUNCTIONAL DESCRIPTION .......................................................................................................29

8.1 P

ROCESSOR

NTERFACE

...............................................................................................................................29

8.1.1 Read-Write/Data Strobe Modes..........................................................................................................30

8.1.2 Clear on Read.....................................................................................................................................30

8.1.3 Interrupt and Pin Modes .....................................................................................................................30

8.2 SPI S

ERIAL

EEPROM I

NTERFACE

................................................................................................................30

8.3 CLOCK STRUCTURE ...............................................................................................................................31

8.3.1 Serial Interface Clock Modes..............................................................................................................33

8.3.2 Ethernet Interface Clock Modes .........................................................................................................33

8.4 R

ESETS

OWER

ODES

................................................................................................................34

8.5 I

NITIALIZATION AND

ONFIGURATION

.............................................................................................................35

8.6 G

LOBAL

ESOURCES

...................................................................................................................................35

8.7 P

-P

ORT

ESOURCES

...............................................................................................................................35

8.8 D

EVICE

NTERRUPTS

....................................................................................................................................36

8.9 S

ERIAL

NTERFACE

.......................................................................................................................................38

8.10 C

ONNECTIONS AND

UEUES

.........................................................................................................................38

8.11 A

RBITER

......................................................................................................................................................39

8.12 F

LOW

ONTROL

...........................................................................................................................................40

8.12.1 Full-Duplex Flow Control ....................................................................................................................41

8.12.2 Half Duplex Flow control.....................................................................................................................42

8.12.3 Host-Managed Flow control................................................................................................................42

8.13 ETHERNET I

NTERFACE

ORT

.....................................................................................................................43

8.13.1 DTE and DCE Mode ...........................................................................................................................45

8.14 E

THERNET

MAC ..........................................................................................................................................46

8.14.1 MII Mode Options................................................................................................................................48

8.14.2 RMII Mode ..........................................................................................................................................48

8.14.3 PHY MII Management Block and MDIO Interface ..............................................................................49

8.15 BERT..........................................................................................................................................................50

8.15.1 Receive Data Interface .......................................................................................................................50

8.15.2 Repetitive Pattern Synchronization ....................................................................................................51

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DS33Z11 Ethernet Mapper

8.15.3 Pattern Monitoring...............................................................................................................................52

8.15.4 Pattern Generation..............................................................................................................................52

8.16 T

RANSMIT

ACKET

ROCESSOR

...................................................................................................................53

8.17 R

ECEIVE

ACKET

ROCESSOR

.....................................................................................................................54

8.18 X.86 E

NCODING AND

ECODING

...................................................................................................................57

8.19 C

OMMITTED

NFORMATION

ATE

ONTROLLER

..............................................................................................60

8.20 H

ARDWARE

ODE

........................................................................................................................................62

DEVICE REGISTERS .....................................................................................................................66

9.1 R

EGISTER

APS

.....................................................................................................................................67

9.1.1 Global Register Bit Map ......................................................................................................................67

9.1.2 Arbiter Register Bit Map......................................................................................................................68

9.1.3 BERT Register Bit Map.......................................................................................................................68

9.1.4 Serial Interface Register Bit Map ........................................................................................................69

9.1.5 Ethernet Interface Register Bit Map....................................................................................................71

9.1.6 MAC Register Bit Map ........................................................................................................................72

9.2 G

LOBAL

EGISTER

EFINITIONS

...................................................................................................................74

9.3 A

RBITER

EGISTERS

....................................................................................................................................83

9.3.1 Arbiter Register Bit Descriptions.........................................................................................................83

9.4 BERT R

EGISTERS

.......................................................................................................................................84

9.5 S

ERIAL

NTERFACE

EGISTERS

.....................................................................................................................91

9.5.1 Serial Interface Transmit and Common Registers..............................................................................91

9.5.2 Serial Interface Transmit Register Bit Descriptions ............................................................................91

9.5.3 Transmit HDLC Processor Registers .................................................................................................92

9.5.4 X.86 Registers ....................................................................................................................................99

9.5.5 Receive Serial Interface....................................................................................................................101

9.6 E

THERNET

NTERFACE

EGISTERS

..............................................................................................................114

9.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................114

9.6.2 MAC Registers..................................................................................................................................126

FUNCTIONAL TIMING .................................................................................................................142

10.1 F

UNCTIONAL

ERIAL

I/O T

IMING

..................................................................................................................142

10.2 MII

AND

RMII I

NTERFACES

.........................................................................................................................143

10.3 SPI I

NTERFACE

ODE AND

EEPROM P

ROGRAM

EQUENCE

......................................................................145

OPERATING PARAMETERS.......................................................................................................147

HERMAL

HARACTERISTICS

......................................................................................................................148

HETA

-JA

. A

IRFLOW

.............................................................................................................................148

RANSMIT

MII I

NTERFACE

...........................................................................................................................149

ECEIVE

MII I

NTERFACE

.............................................................................................................................150

RANSMIT

RMII I

NTERFACE

........................................................................................................................151

ECEIVE

RMII I

NTERFACE

..........................................................................................................................152

MDIO I

NTERFACE

......................................................................................................................................153

RANSMIT

WAN I

NTERFACE

.......................................................................................................................154

ECEIVE

WAN I

NTERFACE

.........................................................................................................................155

SDRAM T

IMING

.........................................................................................................................................156

AC C

HARACTERISTICS

—M

ICROPROCESSOR

IMING

............................................................................158

EEPROM I

NTERFACE

IMING

.....................................................................................................................161

JTAG I

NTERFACE

IMING

...........................................................................................................................162

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

11.10

11.11

11.12

11.13

JTAG INFORMATION ..................................................................................................................163

12.1 JTAG TAP C

ONTROLLER

TATE

ACHINE

ESCRIPTION

............................................................................163

12.2 I

NSTRUCTION

EGISTER

.............................................................................................................................166

12.2.1 SAMPLE:PRELOAD .........................................................................................................................167

12.2.2 BYPASS............................................................................................................................................167

12.2.3 EXTEST ............................................................................................................................................167

12.2.4 CLAMP..............................................................................................................................................167

12.2.5 HIGHZ ...............................................................................................................................................167

3 of 172

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