time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION, Rev. 00A
08/01/02
1
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 2.5V V
DD
and 1.8V V
DDQ
or 3.3V
DD
and 3.3V V
DDQ
memory systems
containing 134,217 ,728 bits. Internally configured as a
quad-bank DRAM with a synchronous interface. Each
16,777,216-bit bank is organized as 4,096 rows by 256
columns by 16 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
Only partials of the memory array can be selected for Self-
Refresh and the refresh period during Self-Refresh is
progammable in 4 steps which drastically reduces the self
refresh current, depending on the case temperature of the
components in the system application.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
ISSI
®
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during burst
access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A11
DQM
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
16
MODE
REGISTER
11
REFRESH
CONTROLLER
I/O 0-15
SELF
REFRESH
CONTROLLER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
11
DATA OUT
BUFFER
16
16
Vcc/Vcc
Q
GND/GNDQ
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
MEMORY CELL
ARRAY
11
ROW
ADDRESS
LATCH
11
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
8
256K
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
8
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION Rev. 00A
06/01/02
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
ISSI
®
V
DD
I/O0
V
DD
Q
NC
I/O1
V
SS
Q
NC
I/O2
V
DD
Q
NC
I/O3
V
SS
Q
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
I/O7
V
SS
Q
NC
I/O6
V
DD
Q
NC
I/O5
V
SS
Q
NC
I/O4
V
DD
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
A0-A11
A0-A8, A10
BA0, BA1
I/O0 to I/O7
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x 8 Lower Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION Rev. 00A
06/01/02
3
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
PIN CONFIGURATIONS
54-Ball FBGA for x16
ISSI
7
8
9
®
1
2
3
4
5
6
A
Vss
B
I/O14
C
I/O12
D
I/O10
E
I/O8
F
UDQM
G
NC/A12
H
A8
J
Vss
A5
A4
A3
A2
Vss
A7
A6
A0
A1
A10
A11
A9
BA0
BA1
CS
CLK
CKE
CAS
RAS
WE
NC
Vss
VDD
LDQM
I/O7
I/O9
VDDQ
VssQ
I/O6
I/O5
I/O11
VssQ
VDDQ
I/O4
I/O3
I/O13
VDDQ
VssQ
I/O2
I/O1
I/O15
VssQ
VDDQ
I/O0
VDD
PIN DESCRIPTIONS
A0-A11
A0-A8, A10
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x16 Lower Bye, Input/Output Mask
x16 Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION Rev. 00A
06/01/02
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
ISSI
®
V
DD
I/O0
V
DD
Q
I/O1
I/O2
V
SS
Q
I/O3
I/O4
V
DD
Q
I/O5
I/O6
V
SS
Q
I/O7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
I/O15
V
SS
Q
I/O14
I/O13
V
DD
Q
I/O12
I/O11
V
SS
Q
I/O10
I/O9
V
DD
Q
I/O8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
A0-A11
A0-A8, A10
BA0, BA1
I/O0 to I/O15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
V
DD
Vss
V
DDQ
Vss
Q
NC
Write Enable
x16 Lower Bye, Input/Output Mask
x16 Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com —
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