a
FEATURES
Upgrade for ADM696/ADM697, MAX696/MAX697
Specified Over Temperature
Adjustable Low Line Voltage Monitor
Power OK/Reset Time Delay
Reset Assertion Down to 1 V V
CC
Watchdog Timer—100 ms, 1.6 s, or Adjustable
Low Switch On Resistance
0.7 Normal, 7 in Backup
400 nA Standby Current
Automatic Battery Backup Switching (ADM8696)
Fast On-Board Gating of Chip Enable Signals (ADM8697)
Voltage Monitor for Power Fail or Low Battery Warning
Also Available in TSSOP Package
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
V
BATT
V
CC
LL
IN
Microprocessor
Supervisory Circuits
ADM8696/ADM8697
FUNCTIONAL BLOCK DIAGRAMS
BATT ON
V
OUT
LOW LINE
RESET
RESET GENERATOR
RESET
OSC IN
OSC SEL
Qualified for Automotive Applications
TIMEBASE FOR RESET
AND WATCHDOG
WATCHDOG
TIMER
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
OUTPUT (WDO)
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
1.3V
ADM8696
POWER FAIL
OUTPUT (PFO)
GENERAL DESCRIPTION
The ADM8696/ADM8697 supervisory circuits offer complete
single chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include
µP
reset, backup battery switchover, watchdog timer,
CMOS RAM write protection and power failure warning.
The ADM8696/ADM8697 are available in 16-pin DIP and small
outline packages (including TSSOP) and provide the following
functions:
1. Power-On Reset output during power-up, power-down and
brownout conditions. The RESET voltage threshold is
adjustable using an external voltage divider. The
RESET
out-
put remains operational with V
CC
as low as 1 V.
2. A Reset pulse if the optional watchdog timer has not been
toggled within specified time.
3. Separate watchdog timeout and low line status outputs.
4. Adjustable reset and watchdog timeout periods.
5. A 1.3 V threshold detector for power fail warning, low battery
detection or to monitor a power supply other than V
CC
.
6. Battery backup switching for CMOS RAM, CMOS micro-
processor or other low power logic (ADM8696).
7. Write protection of CMOS RAM or EEPROM (ADM8697).
CE
IN
LL
IN
CE
OUT
LOW LINE
RESET
RESET GENERATOR
RESET
OSC IN
OSC SEL
TIMEBASE FOR RESET
AND WATCHDOG
WATCHDOG
TIMER
WATCHDOG
OUTPUT (WDO)
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
1.3V
WATCHDOG
TRANSITION DETECTOR
ADM8697
POWER FAIL
OUTPUT (PFO)
The ADM8696/ADM8697 is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(0.7 mW), extremely fast Chip Enable gating (2 ns) and high re-
liability.
RESET
assertion is guaranteed with V
CC
as low as 1 V.
In addition, the power switching circuitry is designed for mini-
mal voltage drop thereby permitting increased output current drive
of up to 100 mA without the need for an external pass transistor.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
©1997-2010 Analog Devices, Inc. All rights reserved.
Fax: 617/326-8703
ADM8696/ADM8697–SPECIFICATIONS
P
arameter
V
CC
Operating Voltage Range
V
BATT
Operating Voltage Range
BATTERY BACKUP SWITCHING (ADM8696)
V
OUT
Output Voltage
V
OUT
in Battery Backup Mode
Supply Current (Excludes I
OUT
)
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, – = Charge)
Battery Switchover Threshold
V
CC
– V
BATT
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short Circuit Current
RESET AND WATCHDOG TIMER
Low Line Threshold (LL
IN
)
Reset Timeout Delay
Watchdog Timeout Period, Internal Oscillator
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
Min
3.0
2.0
Typ
(V
CC
= Full Operating Range, V
BATT
= +2.8 V, T
A
= T
MIN
to T
MAX
unless otherwise noted.)
Units
V
V
V
V
V
µA
µA
µA
mV
mV
mV
V
mA
µA
V
ms
s
ms
Cycles
Cycles
ns
ns
ns
mV
V
V
V
V
V
V
V
µA
V
V
V
µA
µA
V
mV
nA
nA
V
V
V
µA
V
V
V
µA
V
V
ns
ns
µA
µA
kHz
kHz
I
OUT
= 1 mA
I
OUT
≤
100 mA
I
OUT
= 250
µA,
V
CC
< V
BATT
– 0.2 V
I
OUT
= 100 mA
V
CC
= 0 V, V
BATT
= 2.8 V
5.5 V > V
CC
> V
BATT
+ 0.2 V
Power-Up
Power-Down
I
SINK
= 3.2 mA
BATT ON = V
OUT
= 2.4 V Sink Current
BATT ON = V
OUT
, V
CC
= 0 V, Source Current
Test Conditions/Comments
Max
5.5
V
CC
– 0 3
V
CC
– 0.005
V
CC
– 0.0025
V
CC
– 0.125
V
CC
– 0.2
V
BATT
– 0.005 V
BATT
– 0.002
115
200
0.4
1
–0.1
70
50
20
0.3
0.5
1.25
35
1.0
70
4032
960
50
100
30
2.5
1.3
50
1.6
100
4063
1011
25
1.35
70
2.25
140
4097
1025
+0.02
RESET
Output Voltage @ V
CC
= +1 V
RESET,
RESET
Output Voltage
3.5
100
4
0.1
0.1
2.7
20
0.4
0.4
LOW LINE, WDO
Output Voltage
3.5
Output Short Circuit Source Current
WDI Input Threshold
1
Logic Low
Logic High
WDI Input Current
–10
POWER FAIL DETECTOR
PFI Input Threshold
PFI–LL
IN
Threshold Difference
PFI Input Current
LL
IN
Input Current
PFO
Output Voltage
1.2
–50
–25
–50
3.5
PFO
Short Circuit Source Current
CHIP ENABLE GATING (ADM8697)
CE
IN
Threshold
3.0
CE
IN
Pull-Up Current
CE
OUT
Output Voltage
V
CC
– 0.5
CE
Propagation Delay
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with Ext. Capacitor
2
4
±
2
5
0
4
1.2
3
1
2.7
10
1
2.7
10
0.4
25
0.8
OSC SEL = HIGH
Long Period
Short Period
Long Period
Short Period
V
IL
= 0.8, V
IH
= 3.75 V, V
CC
= 5 V
V
IL
= 0.8, V
IH
= 3.5 V, V
CC
= 5 V
V
IL
= 0.8, V
IH
= 2.6 V, V
CC
= 3 V
I
SINK
= 10
µA,
V
CC
= 1 V
I
SINK
= 400
µA,
V
CC
= 2 V, V
BATT
= 0 V
I
SINK
= 3.2 mA, 3 V < V
CC
< 5.5 V
I
SOURCE
= 1
µA,
V
CC
= 5 V
I
SOURCE
= 1
µA,
V
CC
= 3 V
I
SINK
= 3.2 mA,
I
SOURCE
= 1
µA,
V
CC
= 5 V
I
SOURCE
= 1
µA,
V
CC
= 3 V
V
CC
= 5 V
3.5
1.2
1
–1
1.3
±
15
±
0.01
±
0.01
10
V
CC
= 5 V
V
CC
= 3 V
WD1 = V
OUT
, (V
CC
)
WD1 = 0 V
1.4
+50
+25
+50
0.4
25
0.8
I
SINK
= 3.2 mA
I
SOURCE
= 1
µA
I
SOURCE
= 1
µA,
V
CC
= 3 V
PFI = Low,
PFO
= 0 V
V
IL
V
IH
V
CC
= 3 V
I
SINK
= 3.2 mA
I
SOURCE
= 800
µA
V
CC
= 5.0 V
V
CC
= 3.0 V
0.4
7
500
OSC SEL = 0 V
OSC SEL = 0 V, C
OSC
= 47 pF
NOTE
1
WDI is a three-level input internally biased to 38% of V
CC
and has an input impedance of approximately 5 MΩ.
Specifications subject to change without notice.
–2–
REV. A
ADM8696/ADM8697
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
V
BATT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V
OUT
+ 0.5 V
Input Current
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
V
BATT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . . 500 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8696/ADM8697 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
V
BATT
V
OUT
V
CC
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
1
2
3
4
5
6
7
8
16 RESET
15 RESET
ADM8696
TOP VIEW
(Not to Scale)
14 WDO
13 LL
IN
12 NC
11 WDI
10 PFO
9
PFI
TEST
NC
V
CC
LL
IN
GND
LOW LINE
OSC IN
OSC SEL
1
2
3
4
5
6
7
8
16 RESET
15 RESET
TOP VIEW
(Not to Scale)
ADM8697
14 WDO
13 CE
IN
12 CE
OUT
11 WDI
10 PFO
9
PFI
REV. A
–3–
ADM8696/ADM8697
PIN FUNCTION DESCRIPTION
Mnemonic
V
CC
V
BATT
V
OUT
Pin No.
ADM8696 ADM8697 Function
3
1
2
3
—
—
Power Supply Input +3 V to +5 V.
Backup Battery Input.
Output Voltage, V
CC
or V
BATT
is internally switched to V
OUT
depending on which is at
the highest potential. When V
CC
is higher than V
BATT
and LL
IN
is higher than the reset
threshold, V
CC
is switched to V
OUT
. When V
CC
is lower than V
BATT
and LL
IN
is below the
reset threshold, V
BATT
is switched to V
OUT
. V
OUT
can supply up to 100 mA to power CMOS
RAM. Connect V
OUT
to V
CC
if V
OUT
and V
BATT
are not used.
0 V. Ground reference for all signals.
Logic Output.
RESET
goes low whenever LL
IN
falls below 1.3 V and remains low for 50 ms
after LL
IN
goes above 1.3 V.
RESET
also goes low for 50 ms if the watchdog timer is en-
abled but not serviced within its timeout period. The
RESET
pulse width can be adjusted as
shown in Table I.
Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
than the watchdog timeout period,
RESET
pulses low and
WDO
goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
less than 1.3 V,
PFO
goes low. Connect PFI to GND or V
OUT
when not used. See Figure 1.
Power Fail Output.
PFO
is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. The comparator is turned off and
PFO
goes low when V
CC
is below
V
BATT
.
Logic Input. The input to the CE gating circuit. Connect to GND or V
OUT
if not used.
Logic Output.
CE
OUT
is a gated version of the
CE
IN
signal.
CE
OUT
tracks
CE
IN
when LL
IN
is above 1.3 V. If LL
IN
is below 1.3 V,
CE
OUT
is forced high.
Logic Output. BATT ON goes high when V
OUT
is internally switched to the V
BATT
input.
It goes low when V
OUT
is internally switched to V
CC
. The output typically sinks 7 mA and
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V
OUT
.
Logic Output.
LOW LINE
goes low when LL
IN
falls below 1.3 V. It returns high as soon as
LL
IN
rises above 1.3 V.
Logic Output. RESET is an active high output. It is the inverse of
RESET.
Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3
µA
internal pull-up. See
Table I and Figure 4.
Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog timeout period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog timeout periods.
Logic Output. The Watchdog Output,
WDO,
goes low if WDI remains either high or low
for longer than the watchdog timeout period.
WDO
is set high by the next transition at
WDI. If WDI is unconnected or at midsupply,
WDO
remains high.
WDO
also goes high
when
LOW LINE
goes low.
No Connect. It should be left open.
Voltage Sensing Input. The voltage on the low line input, LL
IN
, is compared with a 1.3 V
reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a
LOW LINE
output signal. It also generates a
RESET/RESET output. The comparator output also controls the battery switchover circuitry.
This is a special test pin using during device manufacture. It should be connected to GND.
GND
RESET
4
15
5
15
WDI
11
11
PFI
PFO
9
10
9
10
CE
IN
CE
OUT
BATT ON
—
—
5
13
12
—
LOW LINE
6
RESET
OSC SEL
16
8
6
16
8
OSC IN
7
7
WDO
14
14
NC
LL
IN
12
13
2
4
TEST
—
1
–4–
REV. A
ADM8696/ADM8697
CIRCUIT INFORMATION
Battery Switchover Section (ADM8696)
Low Line
RESET
OUTPUT
The battery switchover circuit is designed to switch over to
battery backup in the event of a power failure. When LL
IN
is below the reset threshold and V
CC
is below V
BATT
, then
V
BATT
is switched to V
OUT
.
During normal operation, with V
CC
higher than V
BATT
, V
CC
is
internally switched to V
OUT
via an internal PMOS transistor
switch. This switch has a typical on resistance of 0.7
Ω
and can
supply up to 100 mA at the V
OUT
terminal. V
OUT
is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to V
OUT
. The capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1
µF
or greater may be used.
If the continuous output current requirement at V
OUT
exceeds
100 mA or if a lower V
CC
–V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can directly
drive the base of the external transistor.
A 7
Ω
MOSFET switch connects the V
BATT
input to V
OUT
dur-
ing battery backup. This MOSFET has very low input-to-out-
put differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is typi-
cally 0.4
µA.
The ADM8696 operates with battery voltages from 2.0 V to
V
CC
–0.3 V). High value capacitors, either standard electrolytic
or the farad-size double layer capacitors, can also be used for
short-term memory backup. A small charging current of typi-
cally 10 nA (0.1
µA
max) flows out of the V
BATT
terminal. This
current is useful for maintaining rechargeable batteries in a fully
charged condition. This extends the life of the backup battery
by compensating for its self-discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1
µA)
is safe
for even the smallest lithium cells.
If the battery switchover section is not used, V
BATT
should be
connected to GND and V
OUT
should be connected to V
CC
.
V
CC
V
BATT
GATE DRIVE
100
mV
RESET
is an active low output that provides a
RESET
signal to
the microprocessor whenever the Low Line Input (LL
IN
) is be-
low 1.3 V. The LL
IN
input is normally used to monitor the
power supply voltage. An internal timer holds
RESET
low for
50 ms after the voltage on LL
IN
rises above 1.3 V. This is in-
tended as a power-on
RESET
signal for the processor. It allows
time for the power supply and microprocessor to stabilize. On
power-down, the
RESET
output remains low, with V
CC
as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition.
The LL
IN
comparator has approximately 12 mV of hysteresis
for enhanced noise immunity.
In addition to
RESET,
an active high RESET output is also
available. This is the complement of
RESET
and is useful for
processors requiring an active high RESET.
LL
IN
V2
V1
V2
V1
RESET
t
1
t
1
LOW LINE
t
1
= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 2. Power-Fail Reset Timing
Watchdog Timer
RESET
V
OUT
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a
RESET
pulse is generated. The
ADM8696/ADM8697 may be configured for either a fixed
“short” 100 ms or a “long” 1.6 second timeout period or for an
adjustable timeout period. If the “short” period is selected,
some systems may be unable to service the watchdog timer im-
mediately after a reset, so a “long” timeout is automatically ini-
tiated directly after a reset is issued. The watchdog timer is
restarted at the end of Reset, whether the Reset was caused by
lack of activity on WDI or by LL
IN
falling below the reset
threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after
RESET
has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
700
mV
BATT ON
(ADM8691, ADM8693,
ADM8695, ADM8696)
INTERNAL
SHUTDOWN SIGNAL
WHEN
V
BATT
> (V
CC
+ 0.7V)
Figure 1. Battery Switchover Schematic
REV. A
–5–
Embedded System
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