BUK9840-55
16 March 2016
SO
T2
23
N-channel TrenchMOS logic level FET
Product data sheet
1. General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
2. Features and benefits
•
•
•
AEC Q101 compliant
Electrostatically robust due to integrated protection diodes
Low conduction losses due to low on-state resistance
3. Applications
•
Automotive and general purpose power switching
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 150 °C
T
sp
= 25 °C
T
sp
= 25 °C;
Fig. 4
V
GS
= 5 V; I
D
= 5 A; T
j
= 25 °C
Min
-
-
-
Typ
-
-
-
Max
55
10.7
8.3
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
non-repetitive drain-
source avalanche
energy
-
30
40
mΩ
Avalanche ruggedness
E
DS(AL)S
I
D
= 3.6 A; V
sup
≤ 25 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
-
-
60
mJ
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NXP Semiconductors
BUK9840-55
N-channel TrenchMOS logic level FET
5. Pinning information
Table 2.
Pin
1
2
3
4
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
drain
G
Simplified outline
4
Graphic symbol
D
1
2
3
S
SC-73 (SOT223)
sym116
6. Ordering information
Table 3.
Ordering information
Package
Name
BUK9840-55
BUK9840-55/CU
SC-73
SC-73
Description
plastic surface-mounted package with increased
heatsink; 4 leads
plastic surface-mounted package with increased
heatsink; 4 leads
Version
SOT223
SOT223
Type number
7. Marking
Table 4.
Marking codes
Marking code
94055
xxYWW 94055
Type number
BUK9840-55
BUK9840-55/CU
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
P
tot
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
T
sp
= 25 °C;
Fig. 4
T
sp
= 25 °C
T
sp
= 100 °C
BUK9840-55
All information provided in this document is subject to legal disclaimers.
Conditions
T
j
≥ 25 °C; T
j
≤ 150 °C
R
GS
= 20 kΩ
Min
-
-
-10
-
-
-
Max
55
55
10
8.3
10.7
6.8
Unit
V
V
V
W
A
A
© NXP Semiconductors N.V. 2016. All rights reserved
Product data sheet
16 March 2016
2 / 11
NXP Semiconductors
BUK9840-55
N-channel TrenchMOS logic level FET
Symbol
I
DM
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Parameter
peak drain current
storage temperature
junction temperature
Conditions
T
sp
= 25 °C; pulsed
Min
-
-55
-55
Max
40
150
150
Unit
A
°C
°C
Source-drain diode
source current
peak source current
T
sp
= 25 °C
pulsed; T
sp
= 25 °C
I
D
= 3.6 A; V
sup
≤ 25 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
HBM; C = 100 pF; R = 1.5 kΩ
10
2
I
DM
(A)
10
R
DS(on)
= V
DS
/ I
D
t
p
= 1 µs
10 µs
100 µs
1 ms
40
20
0
-
-
10.7
40
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
-
60
mJ
Electrostatic discharge
V
esd
100
electrostatic discharge voltage
-
2
003aaf255
kV
003aaf254
I
D
(%)
80
60
D.C.
1
10 ms
100 ms
0
40
80
120
T
mb
(°C)
160
10
- 1
10
- 1
1
10
V
DS
(V)
10
2
V
GS
≥ 10 V
Fig. 1.
Normalized continuous drain current as a
function of solder point temperature
Fig. 2.
T
sp
= 25 °C; I
DM
is single pulse
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
BUK9840-55
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved
Product data sheet
16 March 2016
3 / 11
NXP Semiconductors
BUK9840-55
N-channel TrenchMOS logic level FET
100
WDSS
(%)
80
60
40
20
0
003aaf267
P
der
(%)
80
60
40
20
0
100
003aaf253
20
40
60
80
100
120
140
160
T
(mb)
(°C)
0
40
80
120
T
mb
(°C)
160
I
D
= 3.6 A
Fig. 3.
Normalised drain-source non-repetitive
avalanche energy rating; avalanche energy as a
function of mounting base temperature
Fig. 4.
Normalized total power dissipation as a
function of solder point temperature
9. Thermal characteristics
Table 6.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
10
2
Z
th(j-mb)
(K/W)
10 δ = 0.5
0.2
0.1
0.05
1
0.02
10
- 1
0
Conditions
Mounted on any printed-circuit board
Min
-
Typ
12
Max
15
Unit
K/W
R
th(j-a)
Mounted on a printed-circuit
-
120
-
K/W
003aaf256
P
δ=
t
p
T
t
p
10
- 4
10
- 3
10
- 2
t
T
1
10
t
p
(s)
10
- 2
10
- 6
10
- 5
10
- 1
Fig. 5.
Transient thermal impedance from junction to solder point as a function of pulse duration
BUK9840-55
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved
Product data sheet
16 March 2016
4 / 11
NXP Semiconductors
BUK9840-55
N-channel TrenchMOS logic level FET
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C
I
DSS
drain leakage current
V
DS
= 55 V; V
GS
= 0 V; T
j
= 150 °C
V
DS
= 55 V; V
GS
= 0 V; T
j
= 25 °C
I
GSS
gate leakage current
V
GS
= 5 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -5 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 5 V; V
DS
= 0 V; T
j
= 150 °C
V
GS
= -5 V; V
DS
= 0 V; T
j
= 150 °C
R
DSon
drain-source on-state
resistance
gate-source
breakdown voltage
V
GS
= 5 V; I
D
= 5 A; T
j
= 150 °C
V
GS
= 5 V; I
D
= 5 A; T
j
= 25 °C
V
DS
= 0 V; T
j
= 25 °C; I
G
= 1 mA
V
DS
= 0 V; T
j
= 25 °C; I
G
= -1 mA
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
T
j
= 25 °C
Min
55
50
0.6
-
1
-
-
-
-
-
-
-
-
10
10
Typ
-
-
-
-
1.5
-
0.05
0.02
0.02
-
-
-
30
-
-
Max
-
-
-
2.3
2
100
10
1
1
5
5
74
40
-
-
Unit
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mΩ
mΩ
V
V
Static characteristics
V
GS(th)
V
(BR)GSS
Dynamic characteristics
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
g
fs
V
SD
t
rr
Q
r
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
transfer conductance
V
DS
= 25 V; I
D
= 5 A; T
j
= 25 °C
I
S
= 5 A; V
GS
= 0 V; T
j
= 25 °C
I
S
= 5 A; dI
S
/dt = -100 A/µs;
V
GS
= -10 V; V
DS
= 30 V; T
j
= 25 °C
V
DS
= 30 V; R
L
= 3.3 Ω; V
GS
= 5 V;
R
G(ext)
= 10 Ω; T
j
= 25 °C; I
D
= 9 A
-
-
-
-
-
-
-
11
1050
205
110
17
65
70
70
19
1400
245
150
25
100
105
105
-
pF
pF
pF
ns
ns
ns
ns
S
Source-drain diode
source-drain voltage
reverse recovery time
recovered charge
-
-
-
0.85
45
0.3
1.1
-
-
V
ns
µC
BUK9840-55
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved
Product data sheet
16 March 2016
5 / 11
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