531EB1406M00DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531EB1406M00DGR

531EB1406M00DGR: DescriptionLVPECL Output Clock Oscillator, 1406MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531EB1406M00DGR Overview

LVPECL Output Clock Oscillator, 1406MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531EB1406M00DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1406 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Power amplifier circuit with comprehensive compensation

Fever Sanbanax HI-FI

KPY series silicon piezoresistive absolute pressure sensor circuit 02

High-precision adjustable voltage stabilized power supply circuit diagram

Negative output voltage integrated regulated power supply composed of BG602 Part 2

Computer motherboard circuit diagram 440BX_29

ST touch library anti-interference problem: I have made several products using the ST touch library. There are no problems in the office test,but the sensitivity is significantly reduced when it comes to production in the workshop.The total shi...; lygtian stm32/stm8

PIC level change interrupt: I am using PIC16F1823 chip, and I am very distressed that the level change interrupt cannot be accessed. I hope to get help from friends on the forum. The following is my program: #include htc.h #incl...; 3050122050 MCU

Bottom-level development: I am doing wince driver development and bootloader development (under ARM). What preparatory knowledge do I need? Or how do I learn it? Please give me the steps, thank you!...; jw_1001 Embedded System

Solution for MSP430F149 BSL download program failure: When using MSPFET-BSL to download MSP430f149, I always get the message "Programming failed, synchronization error, etc.". I use CH340-USB to serial port, and connect TXD/RXD (P3.4/P3.5), TCK, RST (57P...; 灞波儿奔 Microcontroller MCU

Mobile Phone RF Design Skills (I): 1. What is RF?Answer: RF stands for Radio frequency, which mainly includes wireless transceivers.2. What are the frequencies of mobile phones in the world today (CDMA, GSM, local telephone, PHS, analo...; JasonYoo RF/Wirelessly

WinCE SD card driver???: I would like to ask everyone, in order for WinCE to display the SD drive letter, at what stage does the SD driver run? Is it that the driver only needs to initialize the SD controller correctly and re...; lml198694 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components