a
28-Lead ROM-Based
DSP Motor Controller with Current Sense
ADMC328
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
External
PWMTRIP
Pin
Integrated ADC Subsystem
Five Analog Inputs Plus One Dedicated I
SENSE
Input
Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function
28-Lead SOIC or PDIP Package Options
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives, Automotive
MOTOR TYPES
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
FEATURES
20 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 24-Bit Program Memory RAM
4K 24-Bit Program Memory ROM
512 16-Bit Data Memory RAM
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
Edge Resolution to 50 ns
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1
DAG 2
PROGRAM
ROM
4K 24
PROGRAM
RAM
512 24
MEMORY
BLOCK
DATA
MEMORY
512 16
VREF
2.5V
5
ANALOG
INPUTS
I
SENSE
AMP
& TRIP
16-BIT
3-PHASE
PWM
PROGRAM
SEQUENCER
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
POR
TIMER
SERIAL PORT
SPORT1
9-BIT
PIO
2
8-BIT
AUX
PWM
WATCH-
DOG
TIMER
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADMC328–SPECIFICATIONS
ANALOG-TO-DIGITAL CONVERTER
Parameter
Signal Input
Resolution
1
Linearity Error
2
Zero Offset
2
Channel-to-Channel Comparator Match
2
Comparator Delay
ADC Hi-Level Input Current
2
ADC Lo-Level Input Current
2
(V
DD
= +5 V 5%, GND = 0 V, T
A
= –40 C to +105 C for ADMC328Y, T
A
= –40 C to
+125 C for ADMC328T, CLKIN = 10 MHz, unless otherwise noted)
Min
0.3
–0.4
Typ
Max
3.5
0
12
4
+20
20
10
Unit
V
V
Bits
Bits
mV
mV
ns
µA
µA
Conditions/Comments
V1, V2, VAUX0, VAUX1, VAUX2
I
SENSE
–20
2
0
600
–10
V
IN
= 3.5 V
V
IN
= 0.0 V
NOTES
1
Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.
2
2.44 kHz sample frequency, V1, V2, VAUX0, VAUX1, VAUX2.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Parameter
V
IL
V
IH
V
OL
V
OL
V
OH
I
IL
I
IL
I
IH
I
IH
I
OZH
I
OZL
I
IL
I
DD
I
DD
Lo-Level Input Voltage
Hi-Level Input Voltage
Low Level Output Voltage
1
Low Level Output Voltage
2
High Level Output Voltage
Low Level Input Current
3
Low Level Input Current
High Level Input Current
4
High Level Input Current
Hi-Level Three-State Leakage Current
5
Lo-Level Three-State Leakage Current
5
Lo-Level
PWMTRIP
Current
Supply Current (Idle)
6
Supply Current (Dynamic)
6
Min
2
0.4
0.8
4
–120
–10
90
10
90
–10
–10
32
55
Typ
Max
0.8
Unit
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
mA
Conditions/Comments
I
OL
= 2 mA
I
OL
= 2 mA
I
OH
= –0.5 mA
V
IN
= 0 V
V
IN
= 0 V
V
IN
= V
DD
V
IN
= V
DD
V
IN
= V
DD
V
IN
= 0
@ V
DD
= Max, V
IN
= 0 V
NOTES
1
Output pins PIO0–PIO8, AH, AL, BH, BL, CH, CL.
2
XTAL Pin.
3
Internal Pull-Up,
RESET.
4
Internal Pull-Down,
PWMTRIP,
PIO0–PIO8.
5
Three-stateable pins DT1, RFS1, TFS1, SCLK1.
6
Outputs not Switching.
Specifications subject to change without notice.
CURRENT SOURCE
1
Parameter
Programming Resolution
Default Current
2
Tuned Current
NOTES
1
For ADC Calibration.
2
0.3 V to 3.5 V ICONST Voltage.
Specifications subject to change without notice.
Min
70
95
Typ
83
100
Max
3
95
105
Unit
Bits
µA
µA
Conditions/Comments
ICONST_TRIM = 0x00
–2–
REV. B
ADMC328
TIMING PARAMETERS
Parameter
Clock Signals
Signal t
CK
is defined as 0.5 t
CKIN
. The ADMC328 uses an input clock with a
frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz). When
t
CK
values are within the range of 0.5 t
CKIN
period, they should be substituted for
all relevant timing parameters to obtain specification value.
Example: t
CKH
= 0.5 t
CK
– 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.
Timing Requirements:
t
CKIN
CLKIN Period
t
CKIL
CLKIN Width Low
t
CKIH
CLKIN Width High
Switching Characteristics:
t
CKL
CLKOUT Width Low
t
CKH
CLKOUT Width High
t
CKOH
CLKIN High to CLKOUT High
Control Signals
Timing Requirement:
t
RSP
RESET
Width Low
PWM Shutdown Signals
Timing Requirement:
t
PWMTPW
PWMTRIP
Width Low
NOTES
1
Applies after power-up sequence is complete.
Specifications subject to change without notice.
t
CKIN
t
CKIH
CLKIN
Min
Max
Unit
100
20
20
0.5 t
CK
– 10
0.5 t
CK
– 10
0
150
ns
ns
ns
ns
ns
ns
20
5 t
CK1
ns
t
CK
ns
t
CKIL
t
CKOH
t
CKH
CLKOUT
t
CKL
Figure 1. Clock Signals
–4–
REV. B
Linux and Android
京公网安备 11010802033920号
EEWORLD
