M95640
M95320
64Kbit and 32Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
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Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
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Figure 1. Packages
Single Supply Voltage:
– 4.5V to 5.5V for M95xxx
– 2.5V to 5.5V for M95xxx-W
– 1.8V to 3.6V for M95xxx-S
8
1
PDIP8 (BN)
0.25 mm frame
s
10MHz, 5MHz or 2MHz clock rate (depending
on ordering options)
5ms or 10ms Write Time (depending on
ordering options)
Status Register
Hardware Protection of the Status Register
BYTE and PAGE WRITE (up to 32 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
More than 100,000 or 1 million Erase/Write
Cycles (depending on ordering options)
More than 40 Year Data Retention
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s
s
s
s
s
s
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8
1
SO8 (MN)
150 mil width
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TSSOP8 (DW)
169 mil width
TSSOP14 (DL)
169 mil width
March 2003
1/36
M95640, M95320
SUMMARY DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 8192 x 8 bit (M95640), and 4096 x 8
bit (M95320).
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
Figure 2. Logic Diagram
VCC
Figure 3. DIP and SO Connections
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
AI01790D
VCC
HOLD
C
D
Note: 1. See page 30 (onwards) for package dimensions, and how
to identify pin-1.
D
C
S
W
HOLD
M95xxx
Q
Figure 4. TSSOP14 Connections
M95xxx
S
Q
NC
NC
NC
W
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
AI02346C
VSS
AI01789C
VCC
HOLD
NC
NC
NC
C
D
Note: 1. See page 30 (onwards) for package dimensions, and how
to identify pin-1.
2. NC = Not Connected
Table 1. Signal Names
C
D
Q
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Supply Voltage
Ground
S
W
HOLD
V
CC
V
SS
2/36
M95640, M95320
SIGNAL DESCRIPTION
During all operations, V
CC
must be held stable and
within the specified valid range: V
CC
(min) to
V
CC
(max).
All of the input and output signals must be held
High or Low (according to voltages of V
IH
, V
OH
, V
IL
or V
OL
, as specified in Tables 13 to 17). These sig-
nals are described next.
Serial Data Output (Q).
This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D).
This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C).
This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S).
When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by mode. Driving Chip Select (S) Low enables the
device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD).
The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W).
The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write operations.
3/36
M95640, M95320
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 5 shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
Figure 5. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
CS3
CS2
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
SPI Memory
Device
SPI Memory
Device
C Q D
C Q D
AI03746D
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 6, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
4/36
M95640, M95320
Figure 6. SPI Modes Supported
CPOL
CPHA
C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
5/36
Embedded System
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