a
FEATURES
Low Offset Voltage: 50 V max
Low Offset Voltage Drift: 0.5 V/ C max
Very Low Bias Current
25 C: 100 pA max
–55 C to +125 C: 450 pA max
Very High Open-Loop Gain: 2000 V/mV min
Low Supply Current (per Amplifier): 625 A max
Operates from 2 V to 20 V Supplies
High Common-Mode Rejection: 120 dB min
APPLICATIONS
Strain Gage and Bridge Amplifiers
High Stability Thermocouple Amplifiers
Instrumentation Amplifiers
Photo-Current Monitors
High Gain Linearity Amplifiers
Long-Term Integrators/Filters
Sample-and-Hold Amplifiers
Peak Detectors
Logarithmic Amplifiers
Battery-Powered Systems
GENERAL DESCRIPTION
Precision Picoampere Input Current
Quad Operational Amplifier
OP497
PIN CONNECTIONS
16-Lead Wide Body SOIC
(S-Suffix)
OUT A 1
–IN A 2
+IN A 3
V+ 4
+IN B 5
–IN B 6
OUT B 7
NC 8
NC = NO CONNECT
–
+
+
–
–
+
+
–
16 OUT D
15 –IN D
14 +IN D
OP497
13 V–
12 +IN C
11 –IN C
10 OUT C
9 NC
14-Lead Plastic Dip
(P-Suffix)
14-Lead Ceramic Dip
(Y-Suffix)
OUT A 1
–IN A 2
+IN A 3
V+ 4
+IN B 5
–IN B 6
OUT B 7
–
+
+
–
–
+
+
–
14 OUT D
13 –IN D
12 +IN D
The OP497 is a quad op amp with precision performance in the
space-saving, industry standard 16-lead SOlC package. Its com-
bination of exceptional precision with low power and extremely
low input bias current makes the quad OP497 useful in a wide
variety of applications.
Precision performance of the OP497 includes very low offset,
under 50
µV,
and low drift, below 0.5
µV/°C.
Open-loop gain
exceeds 2000 V/mV ensuring high linearity in every application.
Errors due to common-mode signals are eliminated by the OP497’s
common-mode rejection of over 120 dB. The OP497’s power
supply rejection of over 120 dB minimizes offset voltage changes
experienced in battery-powered systems. Supply current of the
OP497 is under 625
µA
per amplifier, and it can operate with
supply voltages as low as
±
2 V.
The OP497 utilizes a superbeta input stage with bias current can-
cellation to maintain picoamp bias currents at all temperatures.
This is in contrast to FET input op amps whose bias currents start
in the picoamp range at 25°C, but double for every 10°C rise in
temperature, to reach the nanoamp range above 85°C. Input bias
current of the OP497 is under 100 pA at 25°C and is under 450
pA over the military temperature range.
Combining precision, low power, and low bias current, the
OP497 is ideal for a number of applications, including instru-
mentation amplifiers, log amplifiers, photo-diode preamplifiers,
and long-term integrators. For a single device, see the OP97; for a
dual device, see the OP297.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
OP497
11 V–
10 +IN C
9 –IN C
8 OUT C
1000
INPUT CURRENT – PA
V
S
= 15V
V
CM
= 0V
100
–I
B
+I
B
I
OS
10
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE – C
Input Bias, Offset Current vs. Temperature
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP497–SPECIFICATIONS
(@ V = 15 V, T = 25 C, unless otherwise noted.)
S
A
Parameter
Symbol
Condition
A
F
Min Typ Max Min Typ Max
20
40
0.2
0.1
30
80
50
100
0.5
40
70
80
0.4
75
150
150
1.0
C/G
Min Typ Max
80 150
120 250
140 300
0.6
1.5
Unit
µV
INPUT CHARACTERISTICS
Offset Voltage
Vos
–40°C
≤
+85°C
–55°C
≤
+125°C
T
MIN
– T
MAX
Average Input Offset
Voltage Drift
Long-Term Input Offset
Voltage Stability
Input Bias Current
TCV
OS
µV/°C
µV/Mo
pA
I
B
V
CM
= 0 V
–40°
≤
T
A
≤
+85°C
–55°
≤
T
A
≤
+125°C
–40°
≤
T
A
≤
+85°C
–55°
≤
T
A
≤
+125°C
V
CM
= OV
–40°
≤
T
A
≤
+85°C
–55°
≤
T
A
≤
+125°C
+ 13
+13
120
114
100
450
0.1
40 150
60 200
110 600
0.3
0.7
30
50
60
0.3
tl4
+13.5
135
120
0.1
60 200
80 300
130 600
0.3
0.7
50
80
90
0.4
+14
+13.5
135
120
Average Input Bias
Current Drift
Input Offset Current
TC
IB
Ios
0.5
15
35
0.2
+14
+13.5
140
130
100
400
150
200
600
200
300
600
pA/°C
pA
Average Input Offset
Current Drift
Input Voltage Range
1
T
C
I
OS
IVR
T
MIN
– T
MAX
V
CM
=
±
13 V
T
MIN
– T
MAX
V
O
=
±
10 V,
R
L
= 2 kΩ
–40°
≤
T
A
≤
+85°C
–55°
≤
T
A
≤
+125°C
Common-Mode Rejection CMR
Large Signal Voltage Gain A
VO
+13
+13
114
108
+13
+13
114
108
pA/°C
V
dB
2000 6000
1200 4000
30
500
3
1500 4000
800 2000
1000 3000
30
500
3
±
13
±
13.7
±
13
±
14
±
13
±
13.5
±
25
114 135
108 120
525
580
±
2
±
2.5
0.05 0.15
500
150
0.3
17
15
20
1200 4000
800 2000
800 3000
30
500
3
±
13
±
13.7V
±
13
±
14
±
13
±
13.5
±
25
114 135
108 120
525 625
580 750
±
2
±
20
±
2.5
±
20
0.05 0.15
500
150
0.3
17
15
20
V/mV
Input Resistance
Differential Mode
Input Resistance
Common Mode
Input Capacitance
R
IN
R
INCM
C
IN
R
L
= 2 kΩ
R
L
= 10 kΩ
T
MIN
– T
MAX
R
L
= 10 kΩ
MΩ
GΩ
pF
OUTPUT CHARACTERISTICS
Output Voltage Swing
V
O
±
13
±
13.7
±
13
±
14
±
13
±
13.5
±
25
120 140
114 130
525
580
±
2
±
2.5
0.05 0.15
500
Short Circuit
POWER SUPPLY
Power Supply
Rejection Ratio
Supply Current
(per Amplifier)
Supply Voltage Range
I
SC
PSRR
Vs =
±
2 V to
±
20 V
Vs =
±
2.5 V to
±
20 V
T
MIN
– T
MAX
No Load
T
MIN
– T
MAX
Operating Range
T
MIN
– T
MAX
mA
dB
µA
V
I
SY
V
S
625
750
±
20
±
20
625
750
±
20
±
20
DYNAMIC PERFORMANCE
Slew Rate
SR
Gain Bandwidth Product GBW
Channel Separation
CS
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
V/µS
kHz
dB
µV/p-p
nV/√Hz
nV/√Hz
fA/√Hz
V
O
= 20 V
p-p,
fo = 10 Hz
150
0.3
17
15
20
e
n p-p
0.1 Hz to 10 Hz
e
n
= 10 Hz
e
n
= 1 kHz
i
n
= 10 Hz
NOTE
1
Guaranteed by CMR Test.
Specifications subject to change without notice.
–2–
REV. D
OP497
ABSOLUTE MAXIMUM RATINGS
1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20 V
Input Voltage
2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 V
Differential Input Voltage
2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
Y Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP497A, C (Y) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP497F, G (Y) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
OP497F, G (P, S) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature
Y Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
Package Type
14-Pin Cerdip (Y)
14-Pin Plastic DIP (P)
16-Pin SOIC (S)
JA
3
JC
Model
OP497AY*
OP497CY*
OP497FP
OP497FS
OP497GP
OP497GS
Temperature
Range
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Description
14-Lead Cerdip
14-Lead Cerdip
14-Lead Plastic DIP
16-Lead SOIC
14-Lead Plastic DIP
16-Lead SOIC
Package
Option
Q-14
Q-14
N-14
R-16
N-14
R-16
*Not
for new design; obsolete April 2002.
For a military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at www.dscc.dla.mil/
programs.milspec./default.asp.
SMD Part Number
5962–9452101M2A*
5962–9452101MCA
ADI Part Number
OP497BRC
OP497BY
Unit
°C/W
°C/W
°C/W
94
76
92
10
33
23
*Not
for new designs; obsolete April 2002.
NOTES
1
Absolute Maximum Ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than
±
20 V, the absolute maximum input voltage is
equal to the supply voltage.
3
HIA is specified for worst-case mounting conditions, i.e.,
JA
is specified for
device in socket for cerdip, P-DIP packages;
JA
is specified for device soldered
to printed circuit board for SOIC package.
DICE CHARACTERISTICS
–
1/4
OP497
+
2k
V
1
20V p–p @ 10Hz
50k
50
–
1/4
OP497
+
V
1
(
V
2
/10000
)
V
2
CHANNEL SEPARATION = 20 log
Channel Separation Test Circuit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP497 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
OP497–Typical Performance Characteristics
(25 C, Vs = 15 V, unless otherwise noted.)
50
T
A
= 25 C
V
S
= 15V
V
CM
= 0V
PERCENTAGE OF UNITS
50
T
A
= 25 C
V
S
= 15V
V
CM
= 0V
PERCENTAGE OF UNITS
60
T
A
= 25 C
V
S
= 15V
V
CM
= 0V
PERCENTAGE OF UNITS
40
40
50
40
30
30
30
20
20
20
10
10
10
0
–100 –80 –60 –40 –20
0
20 40 60 80 100
V
INPUT OFFSET VOLTAGE –
0
–100 –80 –60 –40 –20 0 20 40 60 80 100
INPUT BIAS CURRENT – pA
0
0
10
20
30
40
50
60
INPUT OFFSET CURRENT – pA
TPC 1. Typical Distribution of
Input Offset Voltage
TPC 2. Typical Distribution of
Input Bias Current
TPC 3. Typical Distribution of
Input Offset Current
50
V
S
= 15V
V
CM
= 0V
PERCENTAGE OF UNITS
40
INPUT CURRENT – pA
1000
V
S
= 15V
V
CM
= 0V
70
60
INPUT BIAS CURRENT – pA
50
40
30
20
10
T
A
= 25 C
V
S
= 15V
–I
B
30
100
+I
B
20
–I
B
+I
B
I
OS
10
0
0
0.1
0.2
0.3 0.4 0.5
TCV
OS
– V/ C
0.6
0.7
0.8
10
–75 –50 –25
0
25
50
75
100 125
0
–15
–10
–5
0
5
10
15
TEMPERATURE – C
COMMON-MODE VOLTAGE – Volts
TPC 4. Typical Distribution of
TCV
OS
TPC 5. Input Bias, Offset
Current vs. Temperature
TPC 6. Input Bias Current vs.
Common-Mode Voltage
3
DEVIATION FROM FINAL VALUE –
T
A
= 25 C
V
S
= 15V
V
CM
= 0V
2
V
10000
BALANCED OR UNBALANCED
V
S
= 15V
V
CM
= 0V
V/ C
100
BALANCED OR UNBALANCED
V
S
= 15V
V
CM
= 0V
EFFECTIVE OFFSET VOLTAGE –
V
EFFECTIVE OFFSET VOLTAGE –
1000
10
1
100
–55 C
T
A
125 C
T
A
= +25 C
10
10
1
0
0
1
2
3
4
5
TIME AFTER POWER APPLIED – Minutes
100
1k
10k
100k
1M
10M
0.1
100
1k
SOURCE RESISTANCE –
10k
100k
1M
10M
SOURCE RESISTANCE –
100M
TPC 7. Input Offset Voltage
Warm-Up Drift
TPC 8. Effective Offset Voltage
vs. Source Resistance
TPC 9. Effective TCV
OS
vs.
Source Resistance
–4–
REV. D
OP497
1000
10
VOLTAGE NOISE DENSITY – nV/
Hz
CURRENT NOISE DENSITY – fA /
Hz
V/
Hz
T
A
= 25 C
V
S
= 2V TO 20V
T
A
= 25 C
V
S
= 2V TO
20V
5mV
1s
NOISE VOLTAGE – 100mV/DIV
100
90
CURRENT NOISE
VOLTAGE NOISE
10
TOTAL NOISE DENSITY –
100
1
10Hz
1kHz
0.1
10
0%
V
S
= 15V
T
A
= 25 C
1
1
10
100
FREQUENCY – Hz
1000
0.01
10
2
10
3
10
4
10
5
10
6
10
7
0
2
SOURCE RESISTANCE –
4
6
TIME – Secs
8
10
TPC 10. Voltage Noise Density
vs. Frequency
TPC 11. Total Noise Density vs.
Source Resistance
TPC 12. 0.1 Hz to 10 Hz Noise Voltage
DIFFERENTIAL INPUT VOLTAGE – 10 V/ DIV
100
80
GAIN
OPEN-LOOP GAIN – dB
OPEN - LOOP GAIN – V/ MV
PHASE SHIFT – DEG
60
40
20
0
–20
–40
100
PHASE
V
S
= 15V
C
L
= 30pF
R
L
= 1M
T
A
= 25 C
10000
T
A
= –55 C
T
A
= +25C
R
L
= 2k
V
S
= 15V
V
CN
= 10V
T
A
= +125 C
T
A
= +125 C
1000
90
135
180
225
T
A
= +25 C
T
A
= –55 C
V
S
=
V
O
=
100
1
15V
10V
10
LOAD RESISTANCE – k
20
1k
10k
100k
1M
FREQUENCY – Hz
10M
–15
–10
–5
0
5
10
OUTPUT VOLTAGE – V
15
TPC 13. Open-Loop Gain,
Phase vs. Frequency
TPC 14. Open-Loop Gain vs.
Load Resistance
TPC 15. Open-Loop Gain Linearity
160
160
POWER SUPPLY REJECTION – dB
35
COMMON - MODE REJECTION – dB
140
120
100
80
60
40
20
0
1
10
100
1k
10k
FREQUENCY – Hz
V
S
= 15V
T
A
= 25 C
140
120
100
80
60
40
20
0
+PSR
–PSR
V
S
= 15V
T
A
= 25 C
OUTPUT SWING – V
p-p
30
25
20
15
10
5
0
100
V
S
= 15V
T
A
= 25 C
A
VCL
= +1
1%THD
R
L
= 10k
100k
1M
1
10
100
1k
10k
100k
1M
FREQUENCY – Hz
1k
10k
FREQUENCY – Hz
100k
TPC 16. Common-Mode
Rejection vs. Frequency
TPC 17. Power Supply
Rejection vs. Frequency
TPC 18. Maximum Output
Swing vs. Frequency
REV. D
–5–
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