FNFM-TTL-45J datasheet, PDF - EEWORLD Datasheet

FNFM-TTL-45J: DescriptionPulse Discriminator Delay Line, 1-Func, 1-Tap, True Output, TTL, J LEAD, MODULE-14/4; Categorylogic logic; File Size1014KB，2 Pages; ManufacturerEngineered Components Co.

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FNFM-TTL-45J Overview

Pulse Discriminator Delay Line, 1-Func, 1-Tap, True Output, TTL, J LEAD, MODULE-14/4

Parameter Name	Attribute value
Maker	Engineered Components Co.
Parts packaging code	SOIC
package instruction	SOJ,
Contacts	4
Reach Compliance Code	unknown
Other features	TYP. ICC = 30MA; MAX FAN OUT OF 8 TTL LOAD PER OUTPUT; MAX TEMP. COEFF. CAPTURED
series	F
JESD-30 code	R-XDSO-J4
Logic integrated circuit type	PULSE DISCRIMINATOR DELAY LINE
Number of functions	1
Number of taps/steps	1
Number of terminals	4
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	SOJ
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	7.239 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	TTL
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal pitch	2.54 mm
Terminal location	DUAL
Total delay nominal (td)	45 ns

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